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clock module
CLKMOD1–0, 9-5
clock output (CLKOUT), 9-5, 14-22
EXTAL, 9-4, 14-22
RSTOUTl, 9-5
XTAL, 9-5, 14-22
debug
breakpoint (BKPT), 29-2
breakpoint/test mode select (BKPT/TMS), 14-31
CLKOUT, 29-2
debug data (DDATA3–0), 14-32, 29-2
development serial clock (DSCLK), 29-2
development
serial
(DSCLK/TRST), 14-30
development serial input (DSI), 29-2
development
serial
(DSI/TDI), 14-31
development serial output (DSO), 29-2
development
serial
(DSO/TDO), 14-31
JTAG_EN, 14-30
processor status (PST3–0), 29-2
processor status output (PST3–0), 14-32
test clock (TCLK), 14-31
description by pin, 32-3
DMA timers
timer 0 input (DTIN0), 14-28
timer 0 output (DTOUT0), 14-28
timer 1 input (DTIN1), 14-28
timer 1 output (DTOUT1), 14-28
timer 2 input (DTIN2), 14-28
timer 2 output (DTOUT2), 14-28
timer 3 input (DTIN3), 14-29
timer 3 output (DTOUT3), 14-29
Ethernet
carrier receive sense (ECRS), 14-24
collision (ECOL), 14-24
management data (EMDIO), 14-23
management data clock (EMDC), 14-23
receive clock (ERXCLK), 14-24
receive data 0 (ERXDO), 14-24
receive data 3–1 (ERXD3–1), 14-25
receive data valid (ERXDV), 14-24
receive error (ERXER), 14-25
transmit clock (EXTCLK), 14-23
transmit data 0 (ETXD0), 14-23
transmit data 1–3 (ETXD3–1), 14-24
transmit enable (ETXEN), 14-23
transmit error (ETXER), 14-24
external boot mode, 14-17
FlexCAN
receive (CANRX), 14-26
transmit (CANTX), 14-26
general purpose timers
Index-14
INDEX
clock/test
reset
input/test
data
output/test
data
MCF5282 User's Manual
external clock input (SYNCx), 14-27, 20-4
GPTB3–0, 14-27
GPTn2–0, 20-3
GPTn3, 20-4
GPTx3–0, 14-27
2
I
C
serial clock (SCL), 14-26
serial data (SDA), 14-26
interrupts
IRQ7–1, 14-23
JTAG
JTAG_EN, 31-3
TCLK, 31-4
test
data
input/development
(TDI/DSI), 31-4
test data output/development serial output
(TDO/DSO), 31-5
test mode select/breakpoint (TMS/BKPT), 31-4
test
reset/development
(TRST/DSCLK), 31-4
overview, 14-1
power and reference
V
, 14-33
DD
V
, V
, 14-33
DDA
SSA
V
, V
, 14-33
DDF
SSF
V
, 14-33
DDH
V
, V
, 14-33
DDPLL
SSPLL
V
, 14-33
PP
V
,
, 14-33
RH
VRL
V
, 14-33
SS
V
, 14-33
STBY
QADC
analog input (ANn/ANx), 14-29–14-30
analog power (V
, V
DDA
analog reference (V
, V
RH
dedicated digital I/O port supply (V
external trigger input (ETRIG2–1), 27-6
multiplexed address output (MA1–0), 27-6
multiplexed analog input (ANx), 27-6
port QA analog input (AN56–55, 53–52), 27-4
port QA digital input/output (PQA4–3, 1–0), 27-5
port QB analog input (AN3–0), 27-5
port QB digital I/O (PQB3–0), 27-6
QSPI
chip select (QSPI_CS3–0), 14-25
serial clock (QSPI_CLK), 14-25
summary, 22-2
synchronous serial data input (QSPI_DIN), 14-25
synchronous
serial
(QSPI_DOUT), 14-25
reset controller
reset in (RSTI), 14-22, 28-2
reset out (RSTO), 28-2
SDRAM controller
serial
input
serial
clock
, 27-63
SSA)
), 27-63
RL
), 27-7
DDH
data
output
MOTOROLA
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