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16.2 DMA Request Control (DMAREQC)
The DMAREQC register provides a software-controlled connection matrix for DMA
requests. It logically routes DMA requests from the DMA timers and UARTs to the four
channels of the DMA controller. Writing to this register determines the exact routing of the
DMA request to the four channels of the DMA modules. If DCRn[EEXT] is set and the
channel is idle, the assertion of the appropriate DREQn activates channel n.
31
Field
Reset
R/W
15
Field
DMAC3
Reset
R/W
Figure 16-2. DMA Request Control Register (DMAREQC)
Bits
Name
31–16
—
Reserved. Should be cleared.
15–0
DMACn
DMA Channel n. Each four bit field defines the logical connection between the DMA requestors and that DMA
channel. There are seven possible requesters (4 DMA Timers and 3 UARTs). Any request can be routed to any
of the DMA channels. Effectively, the DMAREQC provides a software-controlled routing matrix of the 7
DMA request signals to the 4 channels of the DMA module. DMAC3 controls DMA channel 3. DMAC2
controls DMA channel 2. DMAC1 controls DMA channel 1. DMAC0 controls DMA channel 0.
1000 UART0.
1001 UART1.
1010 UART2.
0100 DMA Timer 0.
0101 DMA Timer 1.
0110 DMA Timer 2.
0111 DMA Timer 3.
All other values are reserved and will not generate a DMA request.
MOTOROLA
—
0000_0000_0000_0000
12
11
DMAC2
0000_0000_0000_0000
IPSBAR + 0x014
Table 16-1. DMAREQC Field Description
Chapter 16. DMA Controller Module
DMA Request Control (DMAREQC)
20
R/W
8
7
4
DMAC1
R/W
Description
19
16
—
3
0
DMAC0
16-3
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