Chip Select Registers; D[19:18] External Boot Chip Select Configuration - Motorola ColdFire MCF5281 User Manual

CS[6:1] can be used. At reset, the port size function of the external boot chip select is
determined by the logic levels of the inputs on D[19:18]. Table 12-4 and Table 12-4 list the
various reset encodings for the configuration signals multiplexed with D[19:18].
Table 12-4. D[19:18] External Boot Chip Select Configuration
Provided the required address range is in the chip select address register (CSAR0), CS0 can
be programmed to continue decoding for a range of addresses after the CSMR0[V] is set,
after which the external boot chip select can be restored only by a system reset.

12.4 Chip Select Registers

Table 12-5 shows the chip select register memory map. Reading reserved locations returns
zeros.
IPSBAR
[31:24]
Offset
0x00_0080 Chip select address register—bank 0 (CSAR0)
0x00_0084
0x00_0088
0x00_008C Chip select address register—bank 1 (CSAR1)
0x00_0090
0x00_0094
0x00_0098 Chip select address register—bank 2 (CSAR2)
0x00_009C
0x00_00A0
0x00_00A4 Chip select address register—bank 3 (CSAR3)
0x00_00A8
MOTOROLA
D[19:18] Boot Device/Data Port Size
00
01
10
11
Table 12-5. Chip Select Registers
[23:16]
[p. 12-6]
Chip select mask register—bank 0 (CSMR0) [p. 12-7]
1
Reserved
[p. 12-6]
Chip select mask register—bank 1 (CSMR1) [p. 12-7]
1
Reserved
[p. 12-6]
Chip select mask register—bank 2 (CSMR2) [p. 12-7]
1
Reserved
[p. 12-6]
Chip select mask register—bank 3 (CSMR3) [p. 12-7]
Chapter 12. Chip Select Module
Internal (32-bit)
External (16-bit)
External (8-bit)
External (32-bit)
[15:8]
Chip select control register—bank 0 (CSCR0)
Chip select control register—bank 1 (CSCR1)
Chip select control register—bank 2 (CSCR2)
Chip Select Registers
[7:0]
1
Reserved
[p. 12-8]
1
Reserved
[p. 12-8]
1
Reserved
[p. 12-8]
1
Reserved
12-5