Table of Contents
Advertisement
Bit(s)
Name
6
DOZE
5
HALTED
4
OVW
3
PIE
2
PIF
1
RLD
0
EN
19.5.2.2 PIT Modulus Register (PMR)
The 16-bit read/write PMR contains the timer modulus value that is loaded into the PIT
counter when the count reaches 0x0000 and the PCSR[RLD] bit is set.
When the PCSR[OVW] bit is set, PMR is transparent, and the value written to PMR is
immediately loaded into the PIT counter. The prescaler counter is reset anytime a new value
is loaded into the PIT counter and also during reset. Reading the PMR returns the value
written in the modulus latch. Reset initializes PMR to 0xFFFF.
MOTOROLA
Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3)
Table 19-3. PCSR Field Descriptions (continued)
Doze mode bit. The read/write DOZE bit controls the function of the PIT in doze mode. Reset
clears DOZE.
0 PIT function not affected in doze mode
1 PIT function stopped in doze mode
When doze mode is exited, timer operation continues from the state it was in before entering
doze mode.
Halted mode bit. Controls the function of the PIT in halted mode. Reset clears HALTED.
During halted mode, register read and write accesses function normally. When halted mode is
exited, timer operation continues from the state it was in before entering halted mode, but any
updates made in halted mode remain.
0 PIT function not affected in halted mode
1 PIT function stopped in halted mode
Note: Changing the HALTED bit from 1 to 0 during halted mode starts the PIT timer. Likewise,
changing the HALTED bit from 0 to 1 during halted mode stops the PIT timer.
Overwrite. Enables writing to PMR to immediately overwrite the value in the PIT counter.
0 Value in PMR replaces value in PIT counter when count reaches 0x0000.
1 Writing PMR immediately replaces value in PIT counter.
PIT interrupt enable. This read/write bit enables the PIF flag to generate interrupt requests.
0 PIF interrupt requests disabled
1 PIF interrupt requests enabled
PIT interrupt flag. This read/write bit is set when the PIT counter reaches 0x0000. Clear PIF by
writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF.
0 PIT count has not reached 0x0000.
1 PIT count has reached 0x0000.
Reload bit. The read/write reload bit enables loading the value of PMR into the PIT counter
when the count reaches 0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMR on count of 0x0000
PIT enable bit. Enables PIT operation. When the PIT is disabled, the counter and prescaler are
held in a stopped state. This bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
Memory Map and Registers
Description
19-5
Advertisement
Table of Contents
