Connections For External Memory Port Sizes; Accesses By Matches In Csars And Dacrs - Motorola ColdFire MCF5281 User Manual

Chip Select Operation
Table 12-3. Accesses by Matches in CSARs and DACRs
Number of CSCR Matches
0
1
Multiple
0
1
Multiple
0
1
Multiple
12.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See
Section 12.4.1.3 for more information. Figure 12-1 shows the correspondence between the
data bus and the external byte strobe control lines (BS[3:0]). Note that all byte lanes are
driven, although the state of unused byte lanes is undefined.
Figure 12-1. Connections for External Memory Port Sizes
12.3.1.2 External Boot Chip Select Operation
CS0, the external boot chip select, allows address decoding for boot ROM before system
initialization. Its operation differs from other external chip select outputs after system reset.
After system reset, CS0 is asserted for every external access. No other chip select can be
used until the valid bit, CSMR0[V], is set, at which point CS0 functions as configured and
12-4
Number of DACR Matches
0
0
0
1
1
1
Multiple
Multiple
Multiple
BS3
External
D[31:24]
data bus
32-bit port
Byte 0
memory
16-bit port
Byte 0
memory
Byte 2
8-bit port
Byte 0
memory
Byte 1
Byte 2
Byte 3
MCF5282 User's Manual
Type of Access
Defined by CSAR
External, burst-inhibited, 32-bit
Defined by DACRs
BS2 BS1 BS0
D[23:16] D[15:8] D[7:0]
Byte 1 Byte 2 Byte 3
Byte 1
Driven, undefined
Byte 3
Driven, undefined
External
Undefined
Undefined
Undefined
Undefined
Undefined
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