Rte And Format Error Exception; Trap Instruction Exception; Interrupt Exception; Fault-On-Fault Halt - Motorola ColdFire MCF5281 User Manual

Motorola microcontroller user's manual
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Processor Exceptions

2.7.10 RTE and Format Error Exception

When an RTE instruction is executed, the processor first examines the 4-bit format field to
validate the frame type. For a ColdFire core, any attempted RTE execution where the
format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the
format error is created without disturbing the original RTE frame and the stacked PC
pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code
from M68000 applications. On M68000 family processors, the SR was located at the top of
the stack. On those processors, bit 30 of the longword addressed by the system stack pointer
is typically zero. Thus, if an RTE is attempted using this "old" format, it generates a format
error on a ColdFire processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches
the second longword operand, (3) adjusts the stack pointer by adding the format value to
the auto-incremented address after the fetch of the first longword, and then (4) transfers
control to the instruction address defined by the second longword operand within the stack
frame.

2.7.11 TRAP Instruction Exception

The TRAP #n instruction always forces an exception as part of its execution and is useful
for implementing system calls.

2.7.12 Interrupt Exception

Interrupt exception processing includes interrupt recognition and the fetch of the
appropriate vector from the interrupt controller using an IACK cycle. See Chapter 10,
"Interrupt Controller Modules" for details on the interrupt controller.

2.7.13 Fault-on-Fault Halt

If a ColdFire processor encounters any type of fault during the exception processing of
another fault, the processor immediately halts execution with the catastrophic
"fault-on-fault" condition. A reset is required to force the processor to exit this halted state.

2.7.14 Reset Exception

Asserting the reset input signal to the processor causes a reset exception. The reset
exception has the highest priority of any exception; it provides for system initialization and
recovery from catastrophic failure. Reset also aborts any processing in progress when the
reset input is recognized. Processing cannot be recovered.
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MCF5282 User's Manual
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