Uart Auxiliary Control Register (Uacrn); Uart Interrupt Status/Mask Registers (Uisrn/Uimrn); Uacrn Field Descriptions - Motorola ColdFire MCF5281 User Manual

23.3.9 UART Auxiliary Control Register (UACRn)

The UACRs, shown in Figure 23-7, control the input enable.
7
Field
Reset
R/W
Address
Figure 23-10. UART Auxiliary Control Register (UACRn)
Table 23-8 describes UACRn fields.
Bits Name
7–1 — Reserved, should be cleared.
0 IEC Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition
on the CTS input (if UIMRn[COS] = 1).

23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)

The UISRs, shown in Figure 23-11, provide status for all potential interrupt sources. UISRn
contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the
internal interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding
UISRn bit has no effect on the output.
True status is provided in the UISRn regardless of UIMRn
settings. UISRn is cleared when the UART module is reset.
7
UIMR COS
Field
UISR COS
Field
Reset
R/W
Address
Figure 23-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
MOTOROLA
IPSBAR + 0x210 (UACR0), 0x250 (UACR1), 0x290 (UACR2)
Table 23-8. UACRn Field Descriptions
NOTE
6
—
—
Read only for status, write only for mask
IPSBAR + 0x214 (UISR0), 0x254 (UISR1), 0x294 (UISR2)
Chapter 23. UART Modules
—
0000_0000
W
Description
3 2
DB
DB
0000_0000
Register Descriptions
1 0
IEC
1 0
FFULL/RxRDY TxRDY
FFULL/RxRDY TxRDY
23-13