Table of Contents
Advertisement
20.6.6 Gated Time Accumulation Mode
Setting the PAMOD bit configures the PA for gated time accumulation operation. An active
level on the PAI pin enables a divide-by-64 clock to drive the PA. The PA edge bit, PEDGE,
selects low levels or high levels to enable the divide-by-64 clock.
The trailing edge of the active level at the PAI pin sets the PA input flag, PAIF. The PA input
interrupt enable bit, PAI, enables the PAIF flag to generate interrupt requests.
The PAI input and GPT channel 3 use the same pin. To use the
PAI input, disconnect it from the output logic by clearing the
channel 3 output mode and output level bits, OM3 and OL3.
Also clear the channel 3 output compare mask bit, OC3M3.
The PA counter register, GPTPACNT, reflects the number of pulses from the divide-by-64
clock since the last reset.
The GPT prescaler generates the divide-by-64 clock. If the
timer is not active, there is no divide-by-64 clock.
CHANNEL 3 OUTPUT COMPARE
Figure 20-22. Channel 3 Output Compare/Pulse Accumulator Logic
20.6.7 General-Purpose I/O Ports
An I/O pin used by the timer defaults to general-purpose I/O unless an internal function
which uses that pin is enabled.
The PORTTn pins can be configured for either an input capture function or an output
compare function. The IOSn bits in the GPT IC/OC select register configure the PORTTn
pins as either input capture or output compare pins.
The PORTTn data direction register controls the data direction of an input capture pin.
External pin conditions trigger input captures on input capture pins configured as inputs.
MOTOROLA
Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
NOTE
NOTE
PULSE
ACCUMULATOR
OM3
OL3
OC3M3
Functional Description
PAD
20-19
Advertisement
Table of Contents
