Uart Mode Registers 1 (Umr1N) - Motorola ColdFire MCF5281 User Manual

Register Descriptions
Table 23-1. UART Module Memory Map (continued)
IPSBAR Offset
UART0 UART1 UART2
0x23C 0x27C 0x2BC
1
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is,
if channel operation is not disabled, undesirable results may occur.
2
This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or
reception of characters. Register contents may also be changed.
3
Address-triggered commands
UART registers are accessible only as bytes.
Interrupt can mean either an interrupt request asserted to the
CPU or a DMA request.

23.3.1 UART Mode Registers 1 (UMR1n)

The UMR1n registers control configuration. UMR1n can be read or written when the mode
register pointer points to it, at RESET or after a
using UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
7
Field RxRTS RxIRQ/FFULL
Reset
R/W
Address IPSBAR + 0x200 (UART0), 0x240 (UART1), 0x280 (UART2). After UMR1n is read or written, the pointer points to
23-4
[31:24]
2
(Read) Do not access
(Write) UART output port bit reset command
3
registers—(UOP0n ) [p. 23-15]
NOTE
NOTE
6 5
ERR
Figure 23-2. UART Mode Registers 1 (UMR1n)
MCF5282 User's Manual
[23:16]
RESET MODE REGISTER POINTER
4 3
PM PT
0000_0000
R/W
UMR2n.
[15:8] [7:0]
—
—
command
2 1
B/C
MOTOROLA
0