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Low-Power Mode Operation
19.3 Low-Power Mode Operation
This subsection describes the operation of the PIT modules in low-power modes and halted
mode of operation. Low-power modes are described in the Power Management Module.
Table 19-1 shows the PIT module operation in low-power modes, and how it can exit from
each mode.
The low-power interrupt control register (LPICR) in the
System Control Module specifies the interrupt level at or above
which the device can be brought out of a low-power mode.
Table 19-1. PIT Module Operation in Low-power Modes
Low-power Mode
Wait
Doze
Stop
Halted
In wait mode, the PIT module continues to operate as in run mode and can be configured
to exit the low-power mode by generating an interrupt request. In doze mode with the
PCSR[DOZE] bit set, PIT module operation stops. In doze mode with the PCSR[DOZE]
bit cleared, doze mode does not affect PIT operation. When doze mode is exited, the PIT
continues to operate in the state it was in prior to doze mode. In stop mode, the system clock
is absent, and PIT module operation stops.
In halted mode with the PCSR[HALTED] bit set, PIT module operation stops. In halted
mode with the PCSR[HALTED] bit cleared, halted mode does not affect PIT operation.
When halted mode is exited, the PIT continues to operate in its pre-halted mode state, but
any updates made in halted mode remain.
19.4 Signals
The PIT module has no off-chip signals.
19-2
NOTE
PIT Operation
Normal if PCR[WAIT] cleared,
stopped otherwise
Normal if PCR[DOZE] cleared,
stopped otherwise
Stopped
Normal if PCR[HALTED] cleared,
stopped otherwise
MCF5282 User's Manual
Mode Exit
Any IRQx Interrupt at or above level in LPICR
Any IRQx Interrupt at or above level in LPICR
No
No. Any IRQx Interrupt will be serviced upon normal
exit from halted mode
MOTOROLA
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