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Memory Map/Register Definition
7
Field
Reset
R/W:
Address
IPSBAR + 0x10_0037 (PORTTCP/SETTC), 0x10_0038 (PORTTDP/SETTD), 0x10_0039
Figure 26-13. Port Pin Data/Set Data Registers (4-bit)
PORTnP/SETn bits are described in Table 26-5.
Table 26-5. PORTnP/SETn (8-bit, 6-bit, and 4-bit) Field Descriptions
Register
8-bit
7-bit
6-bit
4-bit
7-bit
6-bit
4-bit
26.3.2.4 Port Clear Output Data Registers (CLRn)
Clearing a CLRn register clears the corresponding bits in the PORTn register. Setting it has
no effect. Reading the CLRn register returns 0s.
Most PORTn registers have a full 8-bit implementation, as shown in Figure 26-14. The
remaining PORTn registers use fewer than eight bits. Their bit definitions are shown in
Figure 26-15, Figure 26-16, and Figure 26-17.
The CLRn registers are read/write accessible.
7
Field
CLRn7
Reset
R/W:
Address
IPSBAR + 0x10_003C (CLRA), 0x10_003D (CLRB), 003E (CLRC), 0x10_003F (CLRD), 0x10_0040
(CLRE), 0x10_0041 (CLRF), 0x10_0042 (CLRG), 0x10_0043 (CLRH), 0x10_0044 (CLRJ), 0x10_0045
Figure 26-14. Port Clear Output Data Registers (8-bit)
26-12
—
0000
—
(PORTUAP/SETUA)
Bits
Name
7–0
PORTxnP/SETxn
6–0
5–0
3–0
7
—
7–6
7–4
6
5
CLRn6
CLRn5
(CLRDD), 0x10_0046 (CLREH), 0x10_0047 (CLREL)
MCF5282 User's Manual
4
3
PORTnP3/
PORTnP2/
SETn3
SETn2
Port x Pin Data/Set Data Bits
1 Port x pin state is 1 (read); set corresponding PORTx bit
(write)
0 Port x pin state is 0 (read)
Reserved, should be cleared.
4
3
CLRn4
CLRn3
CLRn2
0000_0000
R/W
2
1
0
PORTnP1/
PORTnP0/
SETn1
SETn0
Current Pin State
R/W
Description
2
1
0
CLRn1
CLRn0
MOTOROLA
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