Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3090

PKTE Programming Concepts
Table 44-26: Protocol Operation Decoding (Continued)
OpGroup Dir
0b01 0
0b01 0
NOTE: For SSL/TLS and SRTP, no header processing is performed in hardware.
Table 44-27: Extended Protocol Operation Decoding
OpGroup Dir
0b11 0
0
0b11 0
0
0b11 0
0
0b11 0
0
0b11 0
0
0b11 0
0
0b11 0
0
Error Code Description
The
PKTE_CTL_STAT
or Target Command Mode (TCM). The
engine is configured for Autonomous Ring Mode (ARM). In both cases, when an operation is started, errors are
reported in the status field (bits [23:16]) of this register or structure element. The Extended Error Codes - Status
Encoding table provides a guide on how to decipher the meaning of the bits that are set when an error occurs.
Extended Error Codes
The following table provides information about the extended errors associated with the PKTE module.
44–42
Outbound
OpCode Operation
0b110 Reserved
0b111 SRTP Out-
bound
Outbound
OpCode Operation
0b000 Reserved
0b001 DTLS Out-
bound
0b010... Reserved
0b011
0b100 Ext. SSL Out-
bound
0b101 Ext. TLS v1.0
Outbound
0b110 Ext. TLS v1.1
Outbound
0b111 Reserved
register is used to configure the packet engine for processing in Direct Host Mode (DHM)
PKTE_CTL_STAT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
OpGroup Dir
0b01 1
0b01 1
OpGroup Dir
0b11 1
0b11 1
0b11 1
0b11 1
0b11 1
0b11 1
0b11 1
structure element in memory is used when the packet
Inbound
OpCode Operation
0b100... Reserved
0b110
0b111 SRTP Inbound
Inbound
OpCode Operation
0b000 Reserved
0b001 DTLS Inbound
0b010... Reserved
0b011
0b100 Ext. SSL In-
bound
0b101 Ext. TLS v1.0
Inbound
0b110 Ext. TLS v1.1
Inbound
0b111 Reserved