Register Writes - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

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POWERED BY RTC V
CLOCKED BY 1 Hz TICK
POWERED BY INTERNAL V
CLOCKED BY SCLK
RST
REG WRITE
PENDING
SET
Figure 18-2. RTC Register Architecture

Register Writes

Writes to all RTC MMRs, except the RTC interrupt status register
(
), are saved in write holding registers and then are synchro-
RTC_ISTAT
nized to the RTC 1 Hz clock. The write pending status bit in
indicates the progress of the write. The write pending status bit is set when
a write is initiated and is cleared when all writes are complete. The falling
edge of the write pending status bit causes the write complete flag in
to be set. This flag can be configured in
RTC_ISTAT
ADSP-BF537 Blackfin Processor Hardware Reference
REG
DD
DD
REG WRITE
HOLDING
MMR WRITE
TO REG
5
WRITE
PENDING
STATUS
WRITE
FALLING
COMPLETE
EDGE DETECT
EVENT
N
N
REG READ
SHADOW
16/32
16/32
PAB
RTC_ICTL
Real-Time Clock
1 Hz
TICK
RTC_ISTAT
16
16
RTC_ISTAT
to cause an
18-7

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