Deep Sleep Mode - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

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Dynamic Power Management Controller

When sleep mode is exited, the processor resumes execution from the pro-

gram counter value present immediately prior to entering sleep mode.

Deep Sleep Mode

Deep sleep mode maximizes power savings by disabling the PLL,

. In this mode, the processor core and all peripherals except the

Real-Time Clock (RTC) are disabled. DMA is not supported in this

Deep sleep mode can be exited only by a hardware reset event or an RTC

interrupt. A hardware reset begins the hardware reset sequence. For more

information about hardware reset, see the ADSP-BF53x/BF56x Blackfin

Processor Programming Reference. An RTC interrupt causes the processor

to transition to active mode, and execution resumes from where the pro-

gram counter was when deep sleep mode was entered. If an interrupt is

also enabled in

deep sleep and the ISR is executed.

Note an RTC interrupt in deep sleep mode automatically resets some

fields of the PLL control register (

When in deep sleep mode, clocking to the SDRAM is turned off.

Before entering deep sleep mode, software should ensure that

important information in SDRAM is saved to a non-volatile mem-

ory and/or the SDRAM is placed into self-refresh mode.

Table 20-5. PLL_CTL Values after RTC Wakeup Interrupt

, the vector is taken immediately after exiting

ADSP-BF537 Blackfin Processor Hardware Reference