Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1165

B3TT[1:0] field, 6-23
B3WAT[3:0] field, 6-23
BA[1:0] pins, 6-33
bandwidth, and memory DMA operations,
5-51
bank activate command, 6-35,
bank activation command,
bank address, 6-64
bank size, 6-26, 6-64
bank size encodings (table),
bank width, 6-26
BASEID[10:0] field, 9-49,
baud rate
SPI, 10-20
UART, 13-6, 13-12
baud rate[15:0] field, 10-41
BCINIT[15:0] field, 5-101
BCOUNT[15:0] field,
BDI bit, 5-100
BDIE bit, 5-44, 5-100
BEF bit, 9-85
BGH pin, 6-8
BG signal, 6-8
BGSTAT bit, 6-8, 6-78,
BI bit, 13-24, 13-25
binary decode, B-4
bin x bit, 8-74, 8-75
bit order, selecting, 12-28
BKPRSEN bit, 8-79
Blackfin Loader File Viewer,
Blackfin processor family
I/O memory space, 1-7
memory architecture,
block, DMA, 5-11
block count, DMA, 5-40
block diagrams
bus hierarchy, 2-3
CAN, 9-3
core, 2-5
ADSP-BF537 Blackfin Processor Hardware Reference
G-1
6-51
6-28
9-53
5-102
6-79
19-59
1-4
block diagrams
core timer, 16-2
DMA controller, 5-5
EBIU, 6-4
general-purpose timers,
interrupt processing,
MAC, 8-3
PLL, 20-3
PPI, 7-2
processor, 1-3, 1-4
RTC, 18-3
SDRAM, 6-58, 6-59
SPI, 10-3
SPORT, 12-6
TWI, 11-2
UART, 13-3
watchdog timer, 17-2
block done interrupt, DMA,
block transfers, DMA,
BMODE[2:0] field, 19-5
BMODE[2:0] pins, 19-4
BMODE pins, 19-1
BOIF bit, 9-25, 9-48
BOIM bit, 9-25, 9-47
BOIS bit, 9-25, 9-47
BOLMT[1:0] field, 8-64,
booting, 19-1 to 19-60
16-bit flash boot mode,
boot block flag processing,
booting a different application,
boot ROM functions,
boot stream, 19-11
bypass mode, 19-34
control bits, 19-14
determining boot stream start addresses,
19-29
from 8-bit flash, 19-36
header, 19-13
host boot scenarios,
IGNORE block, 19-27
Index
(continued)
15-3
4-16
5-44
5-41
8-66
19-40
19-18
19-27
19-27
19-12
I-3