Uart1 Controller Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

UART1 Controller Registers

UART1 Controller Registers
UART1 controller registers (0xFFC0 2000 – 0xFFC0 20FF) are listed in
Table A-16. For UART0 registers, see
Table A-16. UART1 Controller Registers
Memory-mapped
Address
0xFFC0 2000
0xFFC0 2000
0xFFC0 2000
0xFFC0 2004
0xFFC0 2004
0xFFC0 2008
0xFFC0 200C
0xFFC0 2010
0xFFC0 2014
0xFFC0 201C
0xFFC0 2024
A-20
Register Name
UART1_THR
UART1_RBR
UART1_DLL
UART1_DLH
UART1_IER
UART1_IIR
UART1_LCR
UART1_MCR
UART1_LSR
UART1_SCR
UART1_GCTL
ADSP-BF537 Blackfin Processor Hardware Reference
Table A-5 on page
See Page
"UART Transmit Holding Registers" on
page 13-26
"UART Receive Buffer Registers" on
page 13-26
"UART Divisor Latch Registers" on
page 13-30
"UART Divisor Latch Registers" on
page 13-30
"UART Interrupt Enable Registers" on
page 13-28
"UART Interrupt Identification Registers" on
page 13-29
"UART Line Control Registers" on page 13-21
"UART Modem Control Registers" on
page 13-23
"UART Line Status Registers" on page 13-24
"UART Scratch Registers" on page 13-31
"UART Global Control Registers" on
page 13-31
A-4.