Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1182

Index
general-purpose timers,
aborting, 15-25
and startup errors, 15-11
autobaud mode, 15-34
block diagram, 15-3
buffer registers, 15-47
capture mode, 15-7
clock source, 15-5
code examples, 15-52
control bit summary,
counter, 15-6
disable timing, 15-25
disabling, 15-39
enabling, 15-7, 15-36,
error detection, 15-10
EXT_CLK mode, 15-47
external interface, 15-4
features, 15-1
flow diagram for EXT_CLK mode,
15-35
generating maximum frequency,
illegal states, 15-10,
internal interface, 15-6
internal timer structure,
interrupts, 15-6, 15-8, 15-17,
interrupt setup, 15-54
interrupt structure, 15-9
measurement report, 15-28, 15-29,
15-30
non-overlapping clock pulses,
output pad disable, 15-15
overflow, 15-6
periodic interrupt requests,
port setup, 15-52
and PPI, 15-5, 15-23
preventing errors in PWM_OUT mode,
15-48
programming model,
PULSE_HI toggle mode,
PWM mode, 15-7
I-20
15-1 to 15-61
15-50
15-38
15-18
15-11
15-4
15-31
15-58
15-55
15-36
15-18
ADSP-BF537 Blackfin Processor Hardware Reference
PWM_OUT mode,
15-47
registers, 15-37
signal generation, 15-53
single pulse generation,
size of register accesses,
stopping in PWM_OUT mode,
three timers with same period,
timer outputs, 15-4
two timers with non-overlapping clocks,
15-20
waveform generation,
WDTH_CAP mode, 15-26,
WDTH_CAP mode configuration,
15-60
WDTH_CAP mode flow diagram,
15-27
Get_DXE_Address function,
Get_DXE_Address functions,
GIRQ bit, 9-46
glitch filtering, UART,
global interrupt flag register (CAN_GIF),
9-48
global interrupt mask register
(CAN_GIM), 9-47
global interrupts, CAN,
global interrupt status register (CAN_GIS),
9-47
global status register (CAN_STATUS),
9-44
glueless connection, 21-5
GM bit, 10-27, 10-41
GPIO, 1-10, 14-1 to 14-35
assigned to same interrupt channel,
14-18
and booting, 19-19
clearing interrupt condition,
clear registers, 14-13
code examples, 14-34
configuration, 14-10
15-13 to 15-25,
15-15
15-38
15-23
15-19
15-16
15-47
19-33
19-31
13-9
9-24
14-16