Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1052

Phase Locked Loop and Clock Control
As long as the
( ) remain constant, the PLL is locked.
PLL_CTL
Table 20-3. System Clock Ratio
Signal Name
SSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
N = 7–15
If changing the clock ratio via writing a new
PLL_DIV
loss due to
When changing clock frequencies in the PLL, the PLL requires time to
stabilize and lock to the new frequency. The PLL lock count register
( ) defines the number of
PLL_LOCKCNT
processor sets the
ing the PLL programming sequence, the internal PLL lock counter begins
incrementing upon execution of the
increments by 1 each
to the value defined in the
20-6
and control bits in the PLL control register
MSEL DF
Divider Ratio Example Frequency Ratios (MHz)
VCO/SCLK VCO
Reserved N/A
1:1 100
2:1 200
3:1 400
4:1 500
5:1 600
6:1 600
N:1 600
, take care that the enabled peripherals do not suffer data
frequency changes.
SCLK
bit in the
PLL_LOCKED
cycle. When the lock counter has incremented
SCLK
PLL_LOCKCNT
ADSP-BF537 Blackfin Processor Hardware Reference
SCLK
N/A
100
100
133
125
120
100
600/N
SSEL
cycles that occur before the
SCLK
register. When execut-
PLL_STAT
instruction. The lock counter
IDLE
register, the
PLL_LOCKED
value into
bit is set.