Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1147

Glossary
fully associative.
Cache architecture where each line can be placed anywhere in the cache.
glueless.
No external hardware is required.
Harvard architecture.
A processor memory architecture that uses separate buses for program and
data storage. The two buses let the processor fetch a data word and an
instruction word simultaneously.
HLL (High Level Language).
A programming language that provides some level of abstraction above
assembly language, often using English-like statements, where each com-
mand or statement corresponds to several machine instructions.
2
I C.
2
A bus standard specified in the Philips I C Bus Specification version 2.1
dated January 2000.
IDLE.
An instruction that causes the processor to cease operations, holding its
current state until an interrupt occurs. Then, the processor services the
interrupt and continues normal execution.
index.
Address portion that is used to select an array element (for example, line
index).
Index registers.
A Data Address Generator (DAG) register that holds an address and acts
as a pointer to memory.
ADSP-BF537 Blackfin Processor Hardware Reference G-11