Powering Down The Core (Hibernate State) - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Dynamic Power Management Controller
Table 20-10. VLEV Encodings (Cont'd)
VLEV Voltage
1110 1.25 volts
1111 1.30 volts
After changing the voltage level in the
cally enters the active mode when the processor enters the idle state. At
that point the voltage level changes and the PLL relocks with the new volt-
age. After the
PLL_LOCKCNT
state. When changing voltages, a larger
sary than when changing just the PLL frequency. See the processor data
sheet for details.
After the voltage has been changed to the new level, the processor can
safely return to any operational mode so long as the operating parameters,
such as core clock frequency (
processor data sheet for the new operating voltage level.

Powering Down the Core (Hibernate State)

The internal supply regulator for the processor can be shut off by writing
to the
b#00 FREQ
. Furthermore, it sets the internal power supply voltage (V
SCLK
0 V, eliminating any leakage currents from the processor. The internal
supply regulator can be woken up by several user-selectable events, all of
which are controlled in the
• RTC event or assertion of the
( ) control bit. This bit must be set if no other wakeups are
WAKE
enabled.
• External GP event, or PHY event (ADSP-BF536 or ADSP-BF537
only, if PHY is used). On the ADSP-BF536 and ADSP-BF537
Blackfin processors, set the PHY wakeup enable (
20-22
has expired, the part returns to the full on
), are within the limits specified in the
CCLK
bits of the
VR_CTL
VR_CTL
ADSP-BF537 Blackfin Processor Hardware Reference
register, the PLL automati-
VR_CTL
value may be neces-
PLL_LOCKCNT
register. This disables both
register:
pin. Set the wakeup-enable
RESET
and
CCLK
) to
DDINT
) control bit
PHYWE