Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1191

memory DMA
handshake operation,
priority, 5-51
scheduling, 5-51
timing, 5-48
transfer operation, starting,
transfer performance, 2-11,
transfers, 5-2, 5-7
word size, 5-10
memory map, external (figure),
memory-mapped registers, See MMRs
memory-to-memory transfer,
MEN bit, 11-34, 11-36
MERR bit, 11-18, 11-43
MERRM bit, 11-41, 11-42
MFD[3:0] field, 12-21,
MII
communications protocol, setting up,
8-48
management interface,
multiplexing, 8-5
pins, 8-5, 14-3
port H, 14-7
port J, 14-8
minutes[5:0] field, 18-20,
minutes event flag bit,
minutes interrupt enable bit,
MISO pin, 10-4, 10-5, 10-15, 10-17,
10-18, 10-19, 10-27
μ-law companding, 12-24,
MMC, continuous polling,
MMCE bit, 8-43, 8-124
MMCINT bit, 8-95, 8-97
MMC interrupt, 8-40,
MMRs, 1-7
address range, A-1
width, A-1
mode fault error, 10-21,
ADSP-BF537 Blackfin Processor Hardware Reference
(continued)
5-11
5-11
2-12
6-3
5-10
12-67
8-7
18-22
18-21
18-20
12-29
8-44
8-45
10-23
modes
boot, 1-25, 19-34
broadcast, 10-10, 10-17,
multichannel, 12-15
serial port, 12-11
SPI master, 10-17, 10-24
SPI slave, 10-18, 10-26
UART DMA, 13-17
UART non-DMA, 13-15
MODF bit, 10-21, 10-43
MOSI pin, 10-4, 10-5, 10-15, 10-17,
10-18, 10-19, 10-27
moving data, serial port,
MPEG compression, PPI,
MPKE bit, 8-34, 8-82,
MPKS bit, 8-34, 8-82
MPROG bit, 11-14, 11-38
MRB bit, 9-45
MRS command, 6-34,
MSEL[5:0] field, 20-3, 20-4,
MSTR bit, 10-19, 10-41
multibank operation, 6-43
MulticastFramesReceivedOK register,
MulticastFramesXmittedOK register,
multichannel frame, 12-20
multichannel frame delay field,
multichannel mode, 12-15
enable/disable, 12-18
frame syncs, 12-19
SPORT, 12-19
multichannel operation, SPORT,
12-25
multi-DXE, 19-26
MultipleCollisionFrames register,
multiple interrupt sources,
multiple slave SPI systems,
multiplexed SDRAM addressing scheme
figure, 6-28
Index
10-18
12-38
7-39
8-83
6-49
20-26
8-56
8-62
12-21
12-15 to
8-60
4-15
10-10
I-29