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High Frequency Design Considerations
To avoid contention, program the turnaround time (bank transition time)
appropriately in the asynchronous memory bank control registers. This
feature allows software to set the number of clock cycles between these
types of accesses on a bank-by-bank basis. Minimally, the External Bus
Interface Unit (EBIU) provides one cycle for the transition to occur.
High Frequency Design Considerations
Because the processor can operate at very fast clock frequencies, signal
integrity and noise problems must be considered for circuit board design
and layout. The following sections discuss these topics and suggest various
techniques to use when designing and debugging signal processing
systems.
Signal Integrity
In addition to reducing signal length and capacitive loading, critical sig-
nals should be treated like transmission lines.
Capacitive loading and signal length of buses can be reduced by using a
buffer for devices that operate with wait states (for example, SDRAMs).
This reduces the capacitance on signals tied to the zero-wait-state devices,
allowing these signals to switch faster and reducing noise-producing cur-
rent spikes. Extra care should be taken with certain signals such as external
memory, read, write, and acknowledge strobes.
Use simple signal integrity methods to prevent transmission line reflec-
tions that may cause extraneous extra clock and sync signals. Additionally,
avoid overshoot and undershoot that can cause long term damage to input
pins.
Some signals are especially critical for short trace length and usually
require series termination. The
ing series resistance at its driver. SPORT interface signals
21-8
pin should have impedance match-
CLKIN
ADSP-BF537 Blackfin Processor Hardware Reference
,
,
,
TCLK
RCLK
RFS
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