Sportx_Mrcsn Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

SPORT Registers
Once the window size has completed, the channel counter resets to 0 in
preparation for the next frame. Because there are synchronization delays
between
RSCLK
approximate. It is never ahead of the channel being served, but it may lag
behind. See Figure
SPORTx Current Channel Register (SPORTx_CHNL)
RO
SPORT0:
0xFFC0 0834
SPORT1:
0xFFC0 0934
Figure 12-40. SPORTx Current Channel Register

SPORTx_MRCSn Registers

The multichannel selection registers are used to enable and disable indi-
vidual channels. The SPORTx multichannel receive select registers
(
SPORTx_MRCSn
nels. There are four registers, each with 32 bits, corresponding to the 128
channels. Setting a bit enables that channel so that the SPORT selects that
word for receive from the multiple word block of data. For example, set-
ting bit 0 selects word 0, setting bit 12 selects word 12, and so on.
Setting a particular bit in the
receive the word in that channel's position of the datastream; the received
word is loaded into the RX buffer. When the secondary receive side is
12-68
and the processor clock, the channel register value is
12-40.
15 14 13 12 11 10 9
0 0 0 0 0 0 0
, shown in Figure
SPORTx_MRCSn
ADSP-BF537 Blackfin Processor Hardware Reference
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
12-41) specify the active receive chan-
register causes the SPORT to
0
Reset = 0x0000
0
CHNL[9:0] (Current
Channel Indicator)