Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1196

Index
port G
GPIO, 14-6, 14-10
interrupt A channel,
multiplexing, 14-6
peripherals, 14-2, 14-5
and PPI, 7-3, 14-6
SPORT, 14-6
structure, 14-5
PORTG_FER (function enable register),
7-4, 14-9
port H
GPIO, 14-10
and MAC, 8-47, 14-7
MII, 14-7
multiplexing, 14-7
peripherals, 14-3
RMII, 14-7
structure, 14-6
timers, 14-7
PORTH_FER (function enable register),
14-9
port J
CAN, 14-8
and MAC, 8-47
MII, 14-8
multiplexing, 14-8
peripherals, 14-3, 14-8
and SPI, 10-4
SPI, 14-8
SPORT, 14-8
structure, 14-7
TWI, 14-8
port multiplexer control register
(PORT_MUX), 14-9,
PORT_MUX (port multiplexer control
register), 5-6, 7-4, 14-9,
port pins, 10-43, 14-3
port pins, test access, B-2
PORT_PREF0 bit, 3-9
PORT_PREF1 bit, 3-9
I-34
14-19
14-22
14-22
ADSP-BF537 Blackfin Processor Hardware Reference
ports, 1-10
See also ports by name
port width, PPI, 7-28
PORTx_FER (function enable registers),
14-14, 14-23
PORTxIO_BOTH (GPIO set on both
edges registers), 14-27
PORTxIO_CLEAR (GPIO clear registers),
14-25
PORTxIO_DIR (GPIO direction register),
14-23
PORTxIO_EDGE (interrupt sensitivity
registers), 14-27
PORTxIO (GPIO data registers),
PORTxIO_INEN (GPIO input enable
registers), 14-14, 14-24
PORTxIO_MASKA_CLEAR (GPIO
mask interrupt A clear registers),
14-31
PORTxIO_MASKA (GPIO mask
interrupt A registers),
PORTxIO_MASKA_SET (GPIO mask
interrupt A set registers),
PORTxIO_MASKA_TOGGLE (GPIO
mask interrupt A toggle registers),
14-33
PORTxIO_MASKB_CLEAR (GPIO
mask interrupt B clear registers),
14-32
PORTxIO_MASKB (GPIO mask
interrupt B registers),
PORTxIO_MASKB_SET (GPIO mask
interrupt B set registers),
PORTxIO_MASKB_TOGGLE (GPIO
mask interrupt B toggle registers),
14-34
PORTxIO_POLAR (GPIO polarity
registers), 14-26
PORTxIO_SET (GPIO set registers),
14-25
14-24
14-28
14-29
14-28
14-30