Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1193

P
PAB, 2-6
arbitration, 2-6
bus agents (masters, slaves),
clocking, 20-2
and EBIU, 6-5
errors generated by SPORT,
performance, 2-7
PACK_EN bit, 7-27, 7-28
packing, serial port, 12-24
page hit, and SDC, 6-41
page miss, 6-52
page miss, and SDC, 6-41
page size, 6-64
PAL systems, 7-7
PAM bit, 8-64, 8-69
parallel peripheral interface, See PPI
PASR[1:0] field, 6-68,
PASR feature, 6-29
PAUSEMACCtrlFramesReceived register,
8-58
PBF bit, 8-64, 8-68
PC100 SDRAM standard,
PC133 SDRAM controller,
PC133 SDRAM standard,
PCF bit, 8-79
PDWN bit, 20-26
PE bit, 13-24, 13-25
PEN bit, 13-21
performance
DAB, 2-10
DEB, 2-11
DMA, 5-46
EAB, 2-11
general-purpose ports,
memory DMA, 5-47
memory DMA transfers, 2-11,
optimization, DMA,
PAB, 2-7
SDRAM, 6-31
ADSP-BF537 Blackfin Processor Hardware Reference
2-6
12-39
6-70
6-1
1-9
6-1
14-9
2-12
5-44
PERIOD_CNT bit, 15-13, 15-22, 15-28,
15-44, 15-50
period value[15:0] field,
period value[31:16] field,
peripheral access bus, See PAB
peripheral DMA, 5-7
peripheral DMA channels,
peripheral DMA start address registers,
5-82
peripheral DMA transfers,
peripheral error interrupts,
peripheral interrupt request lines,
peripheral interrupts, 4-2, 4-4,
peripheral map registers
(DMAx_PERIPHERAL_MAP),
(MDMA_yy_PERIPHERAL_MAP),
5-71
peripheral pins, default configuration,
14-10
peripherals, 1-1
and buses, 1-2
compatible with SPI,
configuring for an IVG priority,
default mapping to DMA,
and DMA controller,
DMA support, 1-2
enabling, 14-3
interrupt events, 4-11
interrupt generated by,
interrupt IDs, 4-11
interrupts, clearing, 4-23
level-sensitivity of interrupts,
list of, 1-1
mapping to DMA, 4-10,
multiplexing, 14-1
remapping DMA assignment,
switching from DMA to non-DMA,
5-81
timing, 2-4
used to wake from idle,
Index
16-6
16-6
5-45
5-2
5-80
4-2
4-7 to 4-13
5-71
10-2
4-17
5-7
5-34
4-14
4-25
5-49
5-8
4-9
I-31