Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1153

Glossary
NRZI (Non-return-to-Zero Inverted).
A binary encoding scheme in which a 0 is represented by a change in the
signal and a 1 is represented by no change—there is no return to a refer-
ence (0) voltage between encoded bits. This method eliminates the need
for a clock signal.
orthogonal.
The characteristic of being independent. An orthogonal instruction set
allows any register to be used in an instruction that references a register.
PAB.
See Peripheral Access Bus
page size.
The amount of memory which has the same row address and can be
accessed with successive read or write commands without needing to acti-
vate another row.
Parallel Peripheral Interface (PPI).
The PPI is a half-duplex, bidirectional port accommodating up to 16 bits
of data. It has a dedicated clock pin and three multiplexed frame sync
pins.
PC (Program Counter).
A register that contains the address of the next instruction to be executed.
peripheral.
Functional blocks not included as part of the core, and typically used to
support system level operations.
Peripheral Access Bus (PAB).
A bus used to provide access to EBIU memory-mapped registers.
ADSP-BF537 Blackfin Processor Hardware Reference G-17