Index
multiplexing,
14-1
MII and RMII,
8-5
port F,
14-5
port G,
14-6
port H,
14-7
port J,
14-8
PPI,
7-3
MVIP-90,
12-26
N
NAK bit, 11-31,
11-32
NDPH bit,
5-23
NDPL bit,
5-23
NDSIZE[3:0] field, 5-18, 5-74,
legal values,
5-34
next descriptor pointer registers
(DMAx_NEXT_DESC_PTR),
(MDMA_yy_NEXT_DESC_PTR),
5-94
NINT bit,
13-29
no-boot mode,
19-8
no boot on software reset bit,
nominal bit rate, CAN,
nominal bit time, CAN,
no operation command,
NOP command,
6-54
normal frame sync mode,
normal timing, serial port,
NTSC systems,
7-7
O
OctetsReceivedAll register,
OctetsReceivedOK register,
OctetsTransmittedAll register,
OctetsTransmittedOK register,
OE bit,
13-24
off-chip memory,
1-6
off-core accesses,
2-5
offsets, DMA descriptor elements,
I-30
5-76
5-94
19-5
9-11
9-10
6-54
12-35
12-35
8-59
8-55
8-63
8-61
5-19
ADSP-BF537 Blackfin Processor Hardware Reference
OI bit,
5-100
OIE bit,
5-100
onboard regulation, bypassing,
on-chip memory,
1-6
on-chip switching regulator controller,
20-18
open drain drivers,
10-1
open drain outputs,
10-17
open page, 6-35,
G-1
operating modes,
20-8
active, 1-23,
20-9
deep sleep, 1-24,
20-10
full on, 1-23,
20-9
hibernate state, 1-24,
PPI,
7-5
sleep, 1-23,
20-9
transition, 20-11,
20-12
OPSSn bit,
9-73
optimization, of DMA performance,
oscilloscope probes,
21-13
OUT_DIS bit, 15-43, 15-44,
outer loop address increment registers
(DMAx_Y_MODIFY),
(MDMA_yy_Y_MODIFY),
outer loop count registers
(DMAx_Y_COUNT),
(MDMA_yy_Y_COUNT),
OutOfRangeLengthField register,
output delay bit,
20-26
output pad disable, timer,
outputs, programmable pins,
overflow interrupt, DMA,
overwrite protection/single shot
transmission register 1
(CAN_OPSS1),
9-73
overwrite protection/single shot
transmission register 2
(CAN_OPSS2),
9-73
OVR bit, 7-31,
7-33
20-20
20-11
5-44
15-51
5-93
5-93
5-90
5-90
8-57
15-15
21-12
5-44
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