Sport1 Controller Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

SPORT1 Controller Registers

SPORT1 Controller Registers
SPORT1 controller registers (0xFFC0 0900 – 0xFFC0 09FF) are listed in
Table A-10.
Table A-10. SPORT 1 Controller Registers
Memory-mapped
Address
0xFFC0 0900
0xFFC0 0904
0xFFC0 0908
0xFFC0 090C
0xFFC0 0910
0xFFC0 0918
0xFFC0 0920
0xFFC0 0924
0xFFC0 0928
0xFFC0 092C
0xFFC0 0930
0xFFC0 0934
A-14
Register Name
SPORT1_TCR1
SPORT1_TCR2
SPORT1_TCLKDIV
SPORT1_TFSDIV
SPORT1_TX
SPORT1_RX
SPORT1_RCR1
SPORT1_RCR2
SPORT1_RCLKDIV
SPORT1_RFSDIV
SPORT1_STAT
SPORT1_CHNL
ADSP-BF537 Blackfin Processor Hardware Reference
See Page
"SPORTx Transmit Configuration 1 Register"
on page 12-48
"SPORTx Transmit Configuration 2 Register"
on page 12-49
"SPORTx Transmit Serial Clock Divider Reg-
ister" on page 12-64
"SPORTx Transmit Frame Sync Divider Reg-
ister" on page 12-65
"SPORTx Transmit Data Register" on
page 12-60
"SPORTx Receive Data Register" on
page 12-62
"SPORTx Receive Configuration 1 Register"
on page 12-54
"SPORTx Receive Configuration 2 Register"
on page 12-55
"SPORTx Receive Serial Clock Divider Regis-
ter" on page 12-65
"SPORTx Receive Frame Sync Divider Regis-
ter" on page 12-66
"SPORTx Status Register" on page 12-64
"SPORTx Current Channel Register" on
page 12-68