Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1069

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to enable wakeup upon assertion of the
external PHY device. If no external PHY interrupt is needed, or if
using the ADSP-BF534, set this bit to enable a general-purpose
external event via the
bit on the ADSP-BF534.)
• Activity on the
control bit to enable wakeup upon detection of CAN bus activity
on the
CANRX
on page 9-38
If the on-chip supply controller is bypassed, so that V
externally, the only way to power down the core is to remove the external
V
voltage source.
DDINT
When the core is powered down, V
the internal state of the processor is not maintained, with the
exception of the
tion stored internally (memory contents, register contents, and so
on) must be written to a non-volatile storage device prior to remov-
ing power. Be sure to set the drive CKE low during reset (
control bit in
behavior of setting the EBIU pins to their inactive state. Failure to
set this bit results in the
takes the SDRAM out of self-refresh mode, resulting in data decay
in the SDRAM due to loss of refresh rate.
Powering down V
applied to the processor, external pins are maintained at a three-state level,
unless otherwise specified.
ADSP-BF537 Blackfin Processor Hardware Reference
pin. (This is the only functionality of this
PH6
pin. Set the CAN RX wakeup enable (
CANRX
pin. Please see
"CAN Wakeup From Hibernate State"
for more details.
register. Therefore, any critical informa-
VR_CTL
to protect against the default reset state
VR_CTL
pin going high during reset, which
CKE
does not affect V
DDINT
Dynamic Power Management
/
PHY_INT
DDINT
is set to 0 V, and thus
DDINT
. While V
DDEXT
pin by an
PH6
)
CANWE
is sourced
)
CKELOW
is still
DDEXT
20-23

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