Pll Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

PLL Registers

To power down the internal supply:
1. If needed, ensure that the RTC, CAN, and/or PHY are enabled for
wakeup in the
2. Write to
wakeup bit to 1 (
ADSP-BF537, and
set the
CKELOW
3. Execute the PLL reprogramming sequence.
4. When the idle state is reached, V
5. When the processor is woken up, whether by RTC, CAN, or PHY
on the ADSP-BF536 or ADSP-BF537, or by RTC or CAN on the
ADSP-BF534, or by a reset interrupt, the PLL relocks and the boot
sequence defined by the
Failure to allow V
waking up the processor can cause undesired results.
PLL Registers
The user interface to the PLL is through four memory-mapped registers
(MMRs):
• The PLL divide register (
• The PLL control register (
• The PLL status register (
• The PLL lock count register (
20-24
register.
SIC_IWR
, setting the
VR_CTL
,
CANWE PHYWE
,
CANWE WAKE
bit if SDRAM data should be maintained.
BMODE[1:0]
to complete the transition to 0 V before
DDINT
PLL_DIV
PLL_CTL
PLL_STAT
ADSP-BF537 Blackfin Processor Hardware Reference
bits to , and the appropriate
FREQ b#00
, on the ADSP-BF536 or
WAKE
on the ADSP-BF534). Optionally,
will transition to 0 V.
DDINT
pin settings takes effect.
)
)
)
)
PLL_LOCKCNT