Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1189

MAC system control register
(EMAC_SYSCTL),
MAC system status register
(EMAC_SYSTAT),
MAC VLAN1 tag register
(EMAC_VLAN1),
MAC VLAN2 tag register
(EMAC_VLAN2),
MAC wakeup frame control and status
register (EMAC_WKUP_CTL),
MAC wakeup frame filter commands
register (EMAC_WKUP_FFCMD),
8-89
MAC wakeup frame filter CRC0/1 register
(EMAC_WKUP_FFCRC0),
MAC wakeup frame filter CRC2/3 register
(EMAC_WKUP_FFCRC1),
MAC wakeup frameX byte mask registers
(EMAC_WKUP_FFMSKx),
MADDR[6:0] field, 11-37
Magic Packet, 8-34
mailbox configuration register 1
(CAN_MC1), 9-69
mailbox configuration register 2
(CAN_MC2), 9-69
mailbox direction register 1 (CAN_MD1),
9-70
mailbox direction register 2 (CAN_MD2),
9-70
mailboxes, CAN, 9-4
mailbox interrupt mask register 1
(CAN_MBIM1),
mailbox interrupt mask register 2
(CAN_MBIM2),
mailbox interrupts, CAN,
mailbox receive interrupt flag register 1
(CAN_MBRIF1),
mailbox receive interrupt flag register 2
(CAN_MBRIF2),
ADSP-BF537 Blackfin Processor Hardware Reference
8-93
8-95
8-80
8-80
8-81
8-92
8-92
8-84
9-79
9-80
9-23
9-81
9-82
mailbox transmit interrupt flag register 1
(CAN_MBTIF1),
mailbox transmit interrupt flag register 2
(CAN_MBTIF2),
mailbox word 0 register
(CAN_MBxx_DATA0),
mailbox word 1 register
(CAN_MBxx_DATA1),
mailbox word 2 register
(CAN_MBxx_DATA2),
mailbox word 3 register
(CAN_MBxx_DATA3),
mailbox word 4 register
(CAN_MBxx_LENGTH),
mailbox word 5 register
(CAN_MBxx_TIMESTAMP),
mailbox word 6 register
(CAN_MBxx_ID0),
mailbox word 7 register
(CAN_MBxx_ID1),
manual
conventions, -lv
related documents, -l
mapping
default interrupt, 4-11
peripheral to DMA,
master control register
(CAN_CONTROL),
masters
DAB, 2-9
PAB, 2-6
MBDI bit, 5-44, 5-100
MBIMn bit, 9-79, 9-80
MBPTR[4:0] field, 9-44
MBRIFn bit, 9-81, 9-82
MBRIRQ bit, 9-46
MBTIFn bit, 9-80, 9-81
MBTIRQ bit, 9-46
MCCRM[1:0] field, 12-67
MCDRXPE bit, 12-67
Index
9-80
9-81
9-67
9-65
9-63
9-61
9-59
9-57
9-55
9-53
4-10
9-43
I-27