Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1032

Specific Blackfin Boot Modes
information, refer to the data sheet for the device. The on-chip
Boot ROM determines which of the above Atmel DataFlash mem-
ories is connected by reading the status register.
The SPI baud rate register is set to 133, which, when based on a 54 MHz
system clock, results in a 54 MHz/(2 x 133) = 203 kbit/s bit rate.
Figure 19-18 through
master mode boot using a 24-bit addressable SPI memory (25LC640 from
Microchip). The loader file used is the same as shown in
page 19-38.
Initially, the on-chip boot ROM determines the SPI memory type con-
nected–an 8-, 16-, or 24-bit addressable or an Atmel DataFlash.
SPICLK all
PF10 all
MOSI all
0
MISO all
DSP SENDS
READ
COMMAND
(0x03)
* START OF BOOT SEQUENCE
** DSP SENDS ANOTHER BYTE AND SPI MEMORY RESPONDS WITH THE BYTE LOCATED AT ADDRESS 0x0
(WITH A VALUE OF 0x40).
***AFTER THIS ADDRESS BYTE IS SENT, A 16-BIT ADDRESSABLE SPI MEMORY IS PROPERLY ADDRESSED
AND READY TO SEND BACK DATA.
Figure 19-18. SPI Master Mode Boot Sequence: SPI Memory Detection
Sequence
The on-chip boot ROM has detected that a 16-bit addressable SPI mem-
ory is connected at this point. Next, it issues the read command and sends
out address 0x0000 to read in the first 10-byte header for the INIT code
DXE count block.
19-46
Figure 19-21
0
0
1
1
DSP SENDS
DSP SENDS
SECOND
FIRST
ADDRESS ADDRESS
BYTE (0x00)***
BYTE (0x00)
SPI MEMORY DETECTION ROUTINE
ADSP-BF537 Blackfin Processor Hardware Reference
show the boot sequence for an SPI
0
0
0 0
DSP SENDS
ANOTHER
BYTE**
Figure 19-12 on
0
1 0