External Interface - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

External Interface

The watchdog timer does not directly interact with any pins of the chip.
Internal Interface
The watchdog timer is clocked by the system clock
accessed through the 16-bit peripheral access bus PAB. The 32-bit regis-
ters and
WDOG_CNT
operations. Hardware ensures that those accesses are atomic.
When the counter expires, one of three event requests can be generated.
Either a reset or an NMI request is issued to the Core Event Controller
(CEC) or a general-purpose interrupt request is passed to the System
Interrupt Controller (SIC).
Description of Operation
If enabled, the 32-bit watchdog timer counts downward every
If it becomes 0, one of three event requests can be issued to either the
CEC or the SIC. Depending on how the
register is programmed, the event that is generated may be a reset, a
non-maskable interrupt, or a general-purpose interrupt.
The counter value can be read through the 32-bit
register cannot, however, be written directly. Rather, software
WDOG_STAT
writes the watchdog period value into the 32-bit
the watchdog is enabled. Once the watchdog is started, the period value
cannot be altered.
ADSP-BF537 Blackfin Processor Hardware Reference
must always be accessed by 32-bit read/write
WDOG_STAT
Watchdog Timer
. Its registers are
SCLK
bit field in the
WDEV
WDOG_STAT
register before
WDOG_CNT
cycle.
SCLK
WDOG_CTL
register. The
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