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Function Enable Registers (PORTx_FER)
For all bits, 0 - GPIO mode, 1 - Enable peripheral function
Port F:
0xFFC0 3200
Port G:
0xFFC0 3204
Port H:
0xFFC0 3208
Px15
Px14
Px13
Px12
Px11
Px10
Figure 14-10. Function Enable Registers
GPIO Direction Registers (PORTxIO_DIR)
For all bits, 0 - Input, 1 - Output
Port F:
0xFFC0 0730
Port G:
0xFFC0 1530
Port H:
0xFFC0 1730
Px15 Direction
Px14 Direction
Px13 Direction
Px12 Direction
Px11 Direction
Px10 Direction
Figure 14-11. GPIO Direction Registers
ADSP-BF537 Blackfin Processor Hardware Reference
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
General-Purpose Ports
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reset = 0x0000
Px0
Px1
Px2
Px3
Px4
Px5
Px6
Px7
Px8
Px9
Reset = 0x0000
Px0 Direction
Px1 Direction
Px2 Direction
Px3 Direction
Px4 Direction
Px5 Direction
Px6 Direction
Px7 Direction
Px8 Direction
Px9 Direction
14-23
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