Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1014

Booting Process
chosen by the
SPI or TWI memory, this is not possible. Therefore, the on-chip boot
ROM provides special support for these three boot modes.
When a different application (
Blackfin, it should be booted into the processor's internal memory. Pro-
grams do not require simulating the built-in boot kernel—instead, the
original kernel can be reused for this purpose. The boot ROM provides
the proper entry addresses for the three master boot modes. All three func-
tions expect register
be booted resides. For flash boot the following sequence may boot in a
stream that is stored in asynchronous memory bank 1.
#include <defBF537.h>
P0.H = HI(_BOOTROM_Boot_DXE_Flash) ;
P0.L = LO(_BOOTROM_Boot_DXE_Flash) ;
R7.H = HI(0x20100000) ;
R7.L = LO(0x20100000) ;
JUMP (P0) ;
This example assumes that the
function determines whether an 8-bit or a 16-bit memory device is con-
nected. Note that the boot stream may also reside in SRAM or SDRAM
memory.
The SPI master boot from flash version takes two more parameters:
which holds the GPIO on port F that the SPI memory's
to, and which holds the value that is written to the
R5
internally. Since the routine writes this value directly into the
register, other GPIOs on port F might be impacted. The fol-
PORTFIO_DIR
lowing example loads a boot stream from address 0 of an SPI memory
connected to the
#include <defBF537.h> /* provides function entry addresses */
P0.H = HI(_BOOTROM_Boot_DXE_SPI) ;
19-28
pins. In the three master modes that boot from flash,
BMODE
.DXE
to hold the start address where the boot stream to
R7
/* provides function entry addresses */
AMS1
pin:
PF4
ADSP-BF537 Blackfin Processor Hardware Reference
) needs to be booted into a running
/* start of async bank 1 */
/* jump to Boot ROM */
strobe has already been activated. The
,
R6
input connects
CS
register
SPI_BAUD