Twi Fifo Status - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

TWI General Operation

TWI FIFO Status

The fields in the TWI FIFO status register (
state of the FIFO buffers' receive and transmit contents. The FIFO buffers
do not discriminate between master data and slave data. By using the sta-
tus and control bits provided, the FIFO can be managed to allow
simultaneous master and slave operation.
• Receive FIFO status (
The
RCVSTAT
bytes in the receive FIFO buffer. The status is updated with each
FIFO buffer read using the peripheral data bus or write access by
the receive shift register. Simultaneous accesses are allowed.
[11] The FIFO is full and contains two bytes of data. Either a sin-
gle or double byte peripheral read of the FIFO is allowed.
[10] Reserved
[01] The FIFO contains one byte of data. A single byte peripheral
read of the FIFO is allowed.
[00] The FIFO is empty.
11-16
RCVSTAT[1:0]
field is read only. It indicates the number of valid data
ADSP-BF537 Blackfin Processor Hardware Reference
) indicate the
TWI_FIFO_STAT
)