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Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

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ADSP-BF537 Blackfin

Processor

®

Hardware Reference

Revision 2.0, December 2005

Part Number

82-000555-01

Analog Devices, Inc.

a

One Technology Way

Norwood, Mass. 02062-9106

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Page 1 ADSP-BF537 Blackfin Processor ® Hardware Reference Revision 2.0, December 2005 Part Number 82-000555-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...
Page 2 Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
CONTENTS PREFACE Purpose of This Manual ............... xliii Intended Audience ............... xliii Manual Contents ................xliv What’s New in This Manual ............xlvii Technical or Customer Support ............ xlvii Supported Processors ..............xlviii Product Information ..............xlix MyAnalog.com ................ xlix Processor Product Information ..........
Page 4 Contents Conventions ..................lv Register Diagram Conventions ..........lvi INTRODUCTION Peripherals ..................1-1 Memory Architecture ..............1-4 Internal Memory ..............1-6 External Memory ..............1-6 I/O Memory Space ..............1-7 DMA Support ................1-7 External Bus Interface Unit ............1-9 PC133 SDRAM Controller .............
Page 5 Contents Clock Signals ................1-22 Dynamic Power Management ............1-23 Full On Mode (Maximum Performance) ........ 1-23 Active Mode (Moderate Power Savings) ........1-23 Sleep Mode (High Power Savings) .......... 1-23 Deep Sleep Mode (Maximum Power Savings) ......1-24 Hibernate State ..............1-24 Voltage Regulation ..............
Page 6 Contents External Access Bus (EAB) ............ 2-10 Arbitration of the External Bus ..........2-11 DEB/EAB Performance ............2-11 MEMORY Memory Architecture ..............3-1 L1 Instruction SRAM ..............3-5 L1 Data SRAM ................3-7 L1 Data Cache ................3-8 Boot ROM ................... 3-8 External Memory ................
Page 7 Contents System Interrupt Controller Registers .......... 4-16 SIC_IARx Registers ............... 4-18 SIC_IMASK Register ............4-20 SIC_ISR Register ..............4-21 SIC_IWR Register ..............4-22 Programming Examples ............... 4-23 Clearing Interrupt Requests ........... 4-23 DIRECT MEMORY ACCESS Overview and Features ..............5-1 DMA Controller Overview ............
Page 8 Contents Variable Descriptor Size ............ 5-18 Mixing Flow Modes ............5-19 Functional Description ............... 5-20 DMA Operation Flow ............5-20 DMA Startup ..............5-20 DMA Refresh ..............5-25 Work Unit Transitions ............5-27 DMA Transmit and MDMA Source ......5-28 DMA Receive ...............
Page 9 Contents Programming Model ..............5-55 Synchronization of Software and DMA ........5-56 Single-buffer DMA Transfers ..........5-58 Continuous Transfers Using Autobuffering ......5-58 Descriptor Structures ............5-60 Descriptor Queue Management ......... 5-61 Descriptor Queue Using Interrupts on Every Descriptor 5-62 Descriptor Queue Using Minimal Interrupts ....
Page 10 Contents DMAx_Y_COUNT/ MDMA_yy_Y_COUNT Registers ......... 5-90 DMAx_CURR_Y_COUNT/ MDMA_yy_CURR_Y_COUNT Registers ..... 5-91 DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY Registers ................ 5-93 DMAx_NEXT_DESC_PTR/ MDMA_yy_NEXT_DESC_PTR Registers ..... 5-94 DMAx_CURR_DESC_PTR/ MDMA_yy_CURR_DESC_PTR Registers ....5-96 HMDMA Registers ............... 5-98 HMDMAx_CONTROL Registers ........5-99 HMDMAx_BCINIT Registers ........5-101 HMDMAx_BCOUNT Registers ........5-101 HMDMAx_ECOUNT Registers ........
Page 11 Contents EXTERNAL BUS INTERFACE UNIT EBIU Overview ................6-1 Block Diagram ................ 6-4 Internal Memory Interfaces ............6-5 Registers .................. 6-6 Shared Pins ................6-6 System Clock ................6-7 Error Detection ............... 6-7 Bus Request and Grant ............6-8 Operation ................6-8 AMC Overview and Features ............
Page 12 Contents AMC Programming Model ............6-18 AMC Registers ................6-21 EBIU_AMGCTL Register ............. 6-21 EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ....6-21 AMC Programming Examples ............. 6-24 SDC Overview and Features ............6-25 Features ................6-25 SDRAM Configurations Supported ........6-26 SDRAM External Bank Size ..........6-27 SDC Address Mapping ............
Page 13 Contents Burst Length ..............6-33 Burst Type ................ 6-34 CAS Latency ..............6-34 Data I/O Mask Function ........... 6-34 SDRAM Commands ............6-34 Mode Register Set (MRS) command ........6-34 Extended Mode Register Set (EMRS) command ....6-34 Bank Activate command ............ 6-35 Read/Write command ............
Page 14 Contents tXSR ................6-38 tREF ................6-39 tREFI ................6-39 SDC Functional Description ............6-39 SDC Operation ..............6-39 SDC Address Muxing ............6-42 Multibank Operation ............6-43 Core and DMA Arbitration ..........6-44 Changing System Clock During Runtime ......6-44 Changing Power Management During Runtime ....
Page 15 Contents Self-Refresh Mode ............. 6-53 Self-Refresh Entry Command ........6-53 Self-Refresh Exit Command ........6-54 No Operation Command ..........6-54 SDC SA10 Pin ..............6-55 SDC Programming Model ............6-55 SDC Configuration ............... 6-56 Example SDRAM System Block Diagrams ......6-58 SDC Register Definitions ............
Page 16 Contents Entire Field ..............7-10 Active Video Only ............7-11 Vertical Blanking Interval (VBI) only ......7-11 ITU-R 656 Output Mode ..........7-12 Frame Synchronization in ITU-R 656 Modes ....7-12 General-Purpose PPI Modes ..........7-13 Data Input (RX) Modes ............ 7-15 No Frame Syncs ............
Page 17 Contents Programming Examples ............... 7-36 Data Transfer Scenarios ............7-39 ETHERNET MAC Overview ..................8-1 Features ................... 8-1 Interface Overview ................ 8-2 External Interface ..............8-4 Clocking ................8-4 Pins ..................8-5 Internal Interface ..............8-6 Power Management ............. 8-7 Description of Operation ..............
Page 18 Contents RX IP Frame Checksum Calculation ......8-21 RX DMA Direction Errors ..........8-22 Transmit DMA Operation ..........8-24 Flexible Descriptor Structure ......... 8-27 TX DMA Data Alignment ..........8-27 Late Collisions .............. 8-28 TX Frame Status Classification ........8-29 TX DMA Direction Errors ..........
Page 19 Contents Configure MAC Registers ............8-48 MAC Address ..............8-48 MII Station Management ..........8-48 Configure PHY ..............8-50 Receive and Transmit Data ............ 8-50 Receiving Data ..............8-51 Transmitting Data ............. 8-51 Ethernet MAC Register Definitions ..........8-51 Control-Status Register Group ..........8-63 EMAC_OPMODE Register ..........
Page 20 Contents System Interface Register Group ..........8-93 EMAC_SYSCTL Register ..........8-93 EMAC_SYSTAT Register ..........8-95 Ethernet MAC Frame Status Registers ........8-97 EMAC_RX_STAT Register ..........8-97 EMAC_RX_STKY Register ..........8-103 EMAC_RX_IRQE Register ..........8-107 EMAC_TX_STAT Register ..........8-108 EMAC_TX_STKY Register ..........8-112 EMAC_TX_IRQE Register ..........
Page 21 Contents CAN Mailbox Control ............. 9-6 CAN Protocol Basics ............... 9-7 CAN Operation ................9-9 Bit Timing ................9-9 Transmit Operation ............... 9-12 Retransmission ..............9-13 Single Shot Transmission ........... 9-15 Auto-Transmission ............9-15 Receive Operation ..............9-15 Data Acceptance Filter ............9-18 Remote Frame Handling ...........
Page 22 Contents Debug and Test Modes ............9-33 Low Power Features ............... 9-37 CAN Built-In Suspend Mode ..........9-37 CAN Built-In Sleep Mode ..........9-38 CAN Wakeup From Hibernate State ......... 9-38 Register Definitions ..............9-39 Global Registers ..............9-42 CAN_CONTROL Register ..........9-43 CAN_STATUS Register ...........
Page 23 Contents Mailbox Control Registers ............. 9-68 CAN_MCx Registers ............9-69 CAN_MDx Registers ............9-70 CAN_RMPx Register ............9-71 CAN_RMLx Register ............9-72 CAN_OPSSx Register ............9-73 CAN_TRSx Registers ............9-74 CAN_TRRx Registers ............9-75 CAN_AAx Register ............9-76 CAN_TAx Register ............9-77 CAN_MBTD Register ............
Page 24 Contents Programming Examples .............. 9-87 CAN Setup Code ..............9-87 Initializing and Enabling CAN Mailboxes ......9-89 Initiating CAN Transfers and Processing Interrupts ....9-90 SPI COMPATIBLE PORT CONTROLLERS Overview ..................10-1 Features ..................10-1 Interface Overview ..............10-3 External Interface ..............10-4 Serial Peripheral Interface Clock Signal (SCK) ....
Page 25 Contents SPI General Operation ............10-17 SPI Control ................. 10-18 Clock Signals ..............10-19 SPI Baud Rate ..............10-20 Error Signals and Flags ............10-20 Mode Fault Error (MODF) ..........10-21 Transmission Error (TXE) ..........10-22 Reception Error (RBSY) ..........10-22 Transmit Collision Error (TXCOL) .........
Page 26 Contents Post Transfer and Next Transfer ........10-47 Stopping ................ 10-48 DMA Transfer ..............10-48 DMA Initialization Sequence .......... 10-49 SPI Initialization Sequence ..........10-50 Starting a Transfer ............10-51 Stopping a Transfer ............10-51 TWO WIRE INTERFACE CONTROLLER Overview ..................11-1 Interface Overview ..............
Page 27 Contents Clock Signal ................ 11-11 Error Signals and Flags ............11-12 TWI Master Status ............11-12 TWI Slave Status ............11-15 TWI FIFO Status ............11-16 TWI Interrupt Status ............11-17 Functional Description ............. 11-20 General Setup ..............11-20 Slave Mode ................11-20 Master Mode Clock Setup ...........
Page 28 Contents TWI_FIFO_CTL Register ..........11-38 TWI_FIFO_STAT Register ..........11-40 TWI_INT_MASK Register ..........11-40 TWI_INT_STAT Register ..........11-43 TWI_XMT_DATA8 Register ..........11-43 TWI_XMT_DATA16 Register ..........11-44 TWI_RCV_DATA8 Register ..........11-45 TWI_RCV_DATA16 Register ..........11-46 Programming Examples ............11-47 Master Mode Setup ............. 11-47 Slave Mode Setup ..............
Page 29 Contents Frame Syncs in Multichannel Mode ......... 12-19 The Multichannel Frame ..........12-20 Multichannel Frame Delay ..........12-21 Window Size ..............12-21 Window Offset ............... 12-22 Other Multichannel Fields in SPORTx_MCMC2 .... 12-22 Channel Selection Register ..........12-23 Multichannel DMA Data Packing ........12-24 Support for H.100 Standard Protocol ........
Page 30 Contents Data Independent Transmit Frame Sync ......12-37 Moving Data Between SPORTs and Memory ....... 12-38 SPORT RX, TX, and Error Interrupts ......... 12-38 PAB Errors ................12-39 Timing Examples ..............12-39 SPORT Registers ..............12-45 Register Writes and Effective Latency ........12-47 SPORTx_TCR1 and SPORTx_TCR2 Registers ....
Page 31 Contents UART PORT CONTROLLERS Overview ..................13-1 Features ..................13-1 Interface Overview ..............13-2 External Interface ..............13-2 Internal Interface ..............13-3 Description of Operation ............13-4 UART Transfer Protocol ............13-4 UART Transmit Operation ............ 13-5 UART Receive Operation ............13-6 IrDA Transmit Operation ............
Page 32 Contents UARTx_RBR Registers ............13-26 UARTx_IER Registers ............13-27 UARTx_IIR Registers ............13-29 UARTx_DLL and UARTx_DLH Registers ......13-30 UARTx_SCR Registers ............13-31 UARTx_GCTL Registers ............ 13-31 Programming Examples ............13-32 GENERAL-PURPOSE PORTS Overview ..................14-1 Features ..................14-2 Interface Overview ..............14-3 External Interface ..............
Page 33 Contents Programming Examples ............. 14-34 GENERAL-PURPOSE TIMERS Overview and Features ..............15-1 Features ................. 15-1 Interface Overview ..............15-2 External Interface ..............15-4 Internal Interface ..............15-6 Description of Operation ............15-6 Interrupt Processing .............. 15-8 Illegal States ................ 15-10 Modes of Operation ..............
Page 34 Contents Timer Registers ................ 15-37 TIMER_ENABLE Register ..........15-38 TIMER_DISABLE Register ..........15-39 TIMER_STATUS Register ..........15-40 TIMERx_CONFIG Registers ..........15-43 TIMERx_COUNTER Registers .......... 15-45 TIMERx_PERIOD and TIMERx_WIDTH Registers ..15-46 Summary ................15-50 Programming Examples ............15-52 CORE TIMER Overview and Features ..............
Page 35 Contents WATCHDOG TIMER Overview and Features ..............17-1 Interface Overview ..............17-2 External Interface ..............17-3 Internal Interface ..............17-3 Description of Operation ............17-3 Register Definitions ..............17-5 WDOG_CNT Register ............17-5 WDOG_STAT Register ............17-6 WDOG_CTL Register ............17-7 Programming Examples ...............
Page 36 Contents Setting Time of Day ............18-12 Using the Stopwatch ............18-13 Interrupts ................18-14 State Transitions Summary ..........18-16 Register Definitions ..............18-19 RTC_STAT Register ............18-20 RTC_ICTL Register ............18-20 RTC_ISTAT Register ............18-21 RTC_SWCNT Register ............18-21 RTC_ALARM Register ............
Page 37 Contents Servicing Reset Interrupts ............19-9 Booting Process ................. 19-11 Header Information ............. 19-13 Host Wait Feedback Strobe (HWAIT) ......19-19 Final Initialization ............19-21 Initialization Code ............... 19-22 Multi-Application (Multi-DXE) Management ...... 19-26 User-callable Boot ROM Functions ......... 19-27 Booting a Different Application ........
Page 38 Contents DYNAMIC POWER MANAGEMENT Phase Locked Loop and Clock Control ........20-1 PLL Overview ............... 20-2 PLL Clock Multiplier Ratios ..........20-3 Core Clock/System Clock Ratio Control ......20-5 Dynamic Power Management Controller ........20-7 Operating Modes ..............20-8 Dynamic Power Management Controller States ...... 20-8 Full On Mode ..............
Page 39 Contents PLL_STAT Register ............. 20-26 PLL_LOCKCNT Register ........... 20-27 VR_CTL Register ..............20-27 Programming Examples ............. 20-28 Active Mode to Full On Mode ..........20-29 Full On Mode to Active Mode ..........20-30 In the Full On Mode, Change CLKIN to VCO Multiplier From 31x to 2x ..........
Page 40 Contents 5 Volt Tolerance ..............21-11 Resetting the Processor ............21-12 Recommendations for Unused Pins ........21-12 Programmable Outputs ............21-12 Test Point Access ..............21-12 Oscilloscope Probes ............. 21-13 Recommended Reading ............21-13 SYSTEM MMR ASSIGNMENTS Dynamic Power Management Registers ......... A-2 System Reset and Interrupt Control Registers ........
Page 41 Contents Handshake MDMA Control Registers ........A-34 Core Timer Registers ..............A-36 Processor-Specific Memory Registers .......... A-36 TEST FEATURES JTAG Standard ................B-1 Boundary-Scan Architecture ............B-2 Instruction Register ..............B-4 Public Instructions ..............B-5 EXTEST – Binary Code 00000 .......... B-5 SAMPLE/PRELOAD –...
Page 42 Contents xlii ADSP-BF537 Blackfin Processor Hardware Reference...
Page 43: Purpose Of This Manual
Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices...
Page 44: Manual Contents
Manual Contents Manual Contents This manual consists of: • Chapter 1, “Introduction” Provides a high level overview of the processor, including peripher- als, power management, and development tools. • Chapter 2, “Chip Bus Hierarchy” Describes on-chip buses, including how data moves through the system.
Page 45 Preface • Chapter 8, “Ethernet MAC” Describes the Ethernet Media Access Controller (MAC) peripheral that is available on ADSP-BF536 and ADSP-BF537 processors. The Ethernet MAC provides a 10/100Mbit/s Ethernet interface, compliant to IEEE Std. 802.3-2002, between an MII (Media Inde- pendent Interface) and the Blackfin peripheral subsystem.
Page 46 Manual Contents • Chapter 15, “General-Purpose Timers” Describes the eight general-purpose timers. • Chapter 16, “Core Timer” Describes the core timer. • Chapter 17, “Watchdog Timer” Describes the watchdog timer. • Chapter 18, “Real-Time Clock” Describes a set of digital watch features of the processor, including time of day, alarm, and stopwatch countdown.
Page 47: What's New In This Manual
Prelimi- nary version of this manual have been made. Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/technicalSupport...
Page 48: Supported Processors
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Supported Processors The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®. Blackfin (ADSP-BFxxx) Processors The name Blackfin refers to a family of 16-bit, embedded processors. VisualDSP++ currently supports the following Blackfin families: ADSP-BF53x and ADSP-BF56x.
Page 49: Product Information
MyAnalog.com is a free feature of the Analog Devices Web site that allows MyAnalog.com customization of a Web page to display only the latest information on products you are interested in.
Page 50: Related Documents
Product Information You may also obtain additional information about Analog Devices and its products in any of the following ways. • E-mail questions or requests for information to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support) • Fax questions or requests for information to...
Page 51: Online Technical Documentation
Preface • VisualDSP++ Assembler and Preprocessor Manual for Blackfin Processors • VisualDSP++ Linker and Utilities Manual for Blackfin Processors • VisualDSP++ Kernel (VDK) User's Guide Visit the Technical Library Web site to access all processor and tools manuals and data sheets: http://www.analog.com/processors/technical_library Online Technical Documentation Online documentation comprises the VisualDSP++ Help system, software...
Page 52: Accessing Documentation From Visualdsp
Product Information If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD-ROM at any time by running the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site.
Page 53: Accessing Documentation From The Web
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit. If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto http://www.analog.com/salesdir...
Page 54: Hardware Tools Manuals
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site. To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site.
Page 55: Conventions
Preface Conventions Text conventions used in this manual are identified and described as follows. Example Description SWRST Software Reset Register names appear in UPPERCASE and a special typeface. The register descriptive names of registers are in mixed case and regular typeface. TMR0E, RESET Pin names appear in UPPERCASE and a special typeface.
Page 56: Register Diagram Conventions
Conventions Register Diagram Conventions Register diagrams use the following conventions: • The descriptive name of the register appears at the top, followed by the short form of the name in parentheses (see Table P-1). • If the register is read-only (RO), write-1-to-set (W1S), or write-1-to-clear (W1C), this information appears under the name.
Page 57 Preface • Bits marked x have an unknown reset value. Consequently, the reset value of registers that contain such bits is undefined or depen- dent on pin values at reset. • Shaded bits are reserved. To ensure upward compatibility with future implementations, write back the value that is read for reserved bits in a register, unless otherwise specified.
Page 58 Conventions Timer Configuration Registers (TIMERx_CONFIG) 15 14 13 12 11 10 Timer0: 0xFFC0 0600 Reset = 0x0000 Timer1: 0xFFC0 0610 TMODE[1:0] (Timer Mode) Timer2: 00 - Reset state - unused 0xFFC0 0620 01 - PWM_OUT mode 10 - WDTH_CAP mode 11 - EXT_CLK mode ERR_TYP[1:0] (Error PULSE_HI...
Page 59: Introduction
1 INTRODUCTION The ADSP-BF534, ADSP-BF536, and ADSP-BF537 processors are new members of the Blackfin processor family that offer significant high per- formance and low power while retaining their ease-of-use benefits. The ADSP-BF536 and ADSP-BF537 processors are completely pin compati- ble, differing only in their performance and on-chip memory, mitigating many risks associated with new product development but allowing the possibility to scale up or down based on specific application demands.
Page 60 Peripherals • Two memory-to-memory DMAs with handshake DMA • Event handler with 32 interrupt inputs • Serial Peripheral Interface (SPI)-compatible • Two UARTs with IrDA® support • Two-Wire Interface (TWI) controller • Eight 32-bit timer/counters with PWM support • Real-Time Clock (RTC) and watchdog timer •...
Page 61 Introduction EVENT JTAG TEST AND WATCHDOG TIMER CONTROLLER/ EMULATION CORE TIMER GPIO PORT VOLTAGE REGULATOR PORT INSTRUCTION DATA SPORT0 MEMORY MEMORY SPORT1 GPIO CORE / SYSTEM BUS INTERFACE PORT UART 0-1 GPIO CONTROLLER PORT TIMERS 0-7 EXTERNAL PORT BOOT ROM FLASH, SDRAM CONTROL Figure 1-1.
Page 62: Memory Architecture
Memory Architecture EVENT JTAG TEST AND WATCHDOG TIMER CONTROLLER/ EMULATION CORE TIMER GPIO PORT ETHERNET MAC VOLTAGE REGULATOR PORT INSTRUCTION DATA SPORT0 MEMORY MEMORY SPORT1 GPIO CORE / SYSTEM BUS INTERFACE PORT UART 0-1 GPIO CONTROLLER PORT TIMERS 0-7 EXTERNAL PORT BOOT ROM FLASH, SDRAM CONTROL...
Page 63 Introduction Table 1-1. Memory Configurations Type of Memory ADSP-BF534 ADSP-BF536 ADSP-BF537 Instruction SRAM/cache, lockable 16K byte 16K byte 16K byte by way or line Instruction SRAM 48K byte 48K byte 48K byte Data SRAM/cache 32K byte 16K byte 32K byte Data SRAM 32K byte 16K byte...
Page 64: Internal Memory
Memory Architecture Internal Memory The processor has three blocks of on-chip memory that provide high bandwidth access to the core: • L1 instruction memory, consisting of SRAM and a 4-way set-asso- ciative cache. This memory is accessed at full processor speed. •...
Page 65: I/O Memory Space
Introduction I/O Memory Space Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Control registers for on-chip I/O devices are mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks: one contains the control MMRs for all core func- tions and the other contains the registers needed for setup and control of the on-chip peripherals outside of the core.
Page 66 DMA Support than the row step size, allowing implementation of interleaved data- streams. This feature is especially useful in video applications where data can be de-interleaved on the fly. Examples of DMA types supported include: • A single, linear buffer that stops upon completion •...
Page 67: External Bus Interface Unit
Introduction External Bus Interface Unit The External Bus Interface Unit (EBIU) on the processor interfaces with a wide variety of industry-standard memory devices. The controller consists of an SDRAM controller and an asynchronous memory controller. PC133 SDRAM Controller The SDRAM controller provides an interface to a single bank of indus- try-standard SDRAM devices or DIMMs.
Page 68: Ports
Ports Ports Because of the rich set of peripherals, the ADSP-BF534, ADSP-BF536, and ADSP-BF537 processor groups the many peripheral signals to four ports—port F, port G, port H, and port J. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls. Eight of the pins (port F7–0) offer high source/high sink current capabilities.
Page 69: Two-Wire Interface
Introduction order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows soft- ware to interrogate the sense of the pins. • GPIO interrupt mask registers – The two GPIO interrupt mask registers allow each individual GPIO pin to function as an inter- rupt to the processor.
Page 70: Controller Area Network
Controller Area Network The TWI externally moves 8-bit data while maintaining compliance with the I C bus protocol. The Philips I C Bus Specification version 2.1 covers many variants of I C. The TWI controller includes these features: • Simultaneous master and slave operation on multiple device systems •...
Page 71 Introduction The interface to the CAN bus is a simple two-wire line. See Figure 9-1 on page 9-2 for a symbolic representation of the CAN transceiver intercon- nection. The Blackfin processor’s output and input pins are CANTX CANRX connected to an external CAN transceiver’s pins, respectively.
Page 72: Ethernet Mac
Ethernet MAC Ethernet MAC The Ethernet Media Access Controller (MAC) peripheral for the ADSP-BF536 and ADSP-BF537 processors provides a 10/100 Mbit/sec- ond Ethernet interface, compliant with IEEE Std. 802.3-2002, between a Media Independent Interface (MII) and the Blackfin peripheral sub- system.
Page 73 Introduction Three distinct ITU-R 656 modes are supported: • Active video only - The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) pre- amble symbols, or any data present during the vertical blanking intervals.
Page 74: Sport Controllers
SPORT Controllers These modes support ADC/DAC connections, as well as video communi- cation with hardware signalling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.
Page 75 Introduction • Framing Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. •...
Page 76: Serial Peripheral Interface (Spi) Port
Serial Peripheral Interface (SPI) Port Serial Peripheral Interface (SPI) Port The processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins and a clock pin.
Page 77: Uart Ports
Introduction The timer units can be used in conjunction with the UARTs to measure the width of the pulses in the datastream to provide an autobaud detect function for a serial channel. The timers can generate interrupts to the processor core to provide peri- odic events for synchronization, either to the processor clock or to a count of external signals.
Page 78: Real-Time Clock
Real-Time Clock dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower priority than most DMA chan- nels because of their relatively low service rates. The UARTs’ baud rate, serial data format, error code generation and sta- tus, and interrupts can be programmed to support: •...
Page 79: Watchdog Timer
Introduction The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60 second counter, a 60 minute counter, a 24 hours counter, and a 32768 day counter.
Page 80: Clock Signals
Clock Signals If configured to generate a hardware reset, the watchdog timer resets both the CPU and the peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog control register.
Page 81: Dynamic Power Management
Introduction Dynamic Power Management The processor provides four operating modes, each with a different perfor- mance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply volt- age to further reduce power dissipation. Control of clocking to each of the peripherals also reduces power consumption.
Page 82: Deep Sleep Mode (Maximum Power Savings)
Voltage Regulation interrupt causes the processor to sense the value of the bypass bit ( BYPASS in the PLL control register ( ). If bypass is disabled, the processor PLL_CTL transitions to the full on mode. If bypass is enabled, the processor transi- tions to the active mode.
Page 83: Boot Modes
Introduction control register ( ) in increments of 50 mV. To reduce standby VR_CTL power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in this state, V can still be applied, eliminating the need for DDEXT external buffers.
Page 84 Boot Modes R/W access times; 4-cycle setup). The boot ROM evaluates the first byte of the boot stream at address 0x2000 0000. If it is 0x40, 8-bit boot is performed. A 0x60 byte is required for 16-bit boot. • Boot from serial SPI memory (EEPROM or flash). Eight-, 16-, or 24-bit addressable devices are supported as well as AT45DB041, AT45DB081, and AT45DB161 data flash devices from Atmel.
Page 85: Instruction Set Description
Introduction • Boot from serial TWI memory (EEPROM/flash) – The Blackfin processor operates in master mode and selects the TWI slave with the unique id 0xA0. It submits successive read commands to the memory device starting at two byte internal address 0x0000 and begins clocking data into the processor.
Page 86 Instruction Set Description small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many fea- tures more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code.
Page 87: Development Tools
Analog Devices emulators and the VisualDSP++ development environment. The same emulator hard- ware that supports other Analog Devices products also fully emulates the ADSP-BF53x processor family. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an...
Page 88 VDK-based objects, and visualizing the system state during application debug. Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspec- tion and modification of memory, registers, and processor stacks.
Page 89 JTAG interface—the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools support- ing the Blackfin processor family. Hardware tools include the ADSP-BF537 EZ-KIT Lite standalone evaluation/development cards.
Page 90 Development Tools 1-32 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 91: Chip Bus Hierarchy
2 CHIP BUS HIERARCHY This chapter discusses on-chip buses, how data moves through the system, and other factors that determine the system organization. Following an overview and a list of key features is a block diagram of the chip bus hier- archy and a description of its operation.
Page 92 Overview The following sections describe the on-chip interfaces between the system and the peripherals via the: • Peripheral Access Bus (PAB) • DMA Access Bus (DAB) • DMA Core Bus (DCB) • DMA External Bus (DEB) • External Access Bus (EAB) The External Bus Interface Unit (EBIU) is the primary chip pin bus and is discussed in Chapter 6, “External Bus Interface...
Page 93: Interface Overview
Chip Bus Hierarchy Interface Overview Figure 2-1 shows the core processor and system boundaries as well as the interfaces between them. CORE L1 MEMORY INSTRUCTION PROCESSOR LOAD DATA CORE CLOCK LOAD DATA (CCLK) DOMAIN STORE DATA SYSTEM CLOCK (SCLK) DOMAIN CORE BUS (DCB) EXTERNAL...
Page 94: Internal Clocks
Interface Overview Internal Clocks The core processor clock ( ) rate is highly programmable with respect CCLK . The rate is divided down from the Phase Locked Loop CLKIN CCLK (PLL) output rate. This divider ratio is set using the parameter of the CSEL PLL divide register.
Page 95 Chip Bus Hierarchy Figure 2-2 shows the core processor and its interfaces to the peripherals and external memory resources. SYSTEM CLOCK DSP ID JTAG AND POWER (8 BITS) MANAGEMENT DEBUG AND JTAG INTERFACE CORE EVENT CONTROLLER POWER AND RESET CLOCK VECTOR CONTROLLER PROCESSOR...
Page 96: Peripheral Access Bus (Pab)
Interface Overview When the instruction request is filled, the 64-bit read can contain a single 64-bit instruction or any combination of 16-, 32-, or 64-bit (partial) instructions. When cache is enabled, four 64-bit read requests are issued to support 32-byte line fill burst operations. These requests are pipelined so that each transfer after the first is filled in a single, consecutive cycle.
Page 97: Pab Performance
Chip Bus Hierarchy • Watchdog timer • Real-time clock (RTC) • Timer 0–7 • SPORT0–1 • SPI • Ports • UART0–1 • PPI • TWI • CAN • Ethernet MAC • Asynchronous memory controller (AMC) • SDRAM controller (SDC) • DMA controller PAB Performance For the PAB, the primary performance criteria is latency, not throughput.
Page 98: Dma Access Bus (Dab), Dma Core Bus (Dcb), Dma External Bus (Deb)
Interface Overview DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB) The DAB, DCB, and DEB buses provide a means for DMA-capable peripherals to gain access to on-chip and off-chip memory with little or no degradation in core bandwidth to memory. DAB Arbitration Sixteen DMA channels and bus masters support the DMA-capable periph- erals in the processor system.
Page 99: Dab Bus Agents (Masters)
Chip Bus Hierarchy Table 2-1. DAB, DCB, and DEB Arbitration Priority DAB, DCB, DEB Master Default Arbitration Priority PPI receive/transmit 0 - highest Ethernet receive Ethernet transmit SPORT0 receive SPORT0 transmit SPORT1 receive SPORT1 transmit SPI receive/transmit UART0 receive UART0 transmit UART1 receive UART1 transmit MDMA stream 0 destination...
Page 100: Dab, Dcb, And Deb Performance
Interface Overview DAB, DCB, and DEB Performance The processor DAB supports data transfers of 16 bits or 32 bits. The data bus has a 16-bit width with a maximum frequency as specified in the pro- cessor data sheet. The DAB has a dedicated port into L1 memory. No stalls occur as long as the core access and the DMA access are not to the same memory bank (4K byte size for L1).
Page 101: Arbitration Of The External Bus
Chip Bus Hierarchy Arbitration of the External Bus Arbitration for use of external port bus interface resources is required because of possible contention between the potential masters of this bus. A fixed-priority arbitration scheme is used. That is, core accesses via the EAB will be of higher priority than those from the DMA external bus (DEB).
Page 102 Interface Overview the form where P0 points to an address in SDRAM). In R0 = W[P0++]; this example, a 32-bit SDRAM read takes 10 cycles while two 16-bit SCLK reads take 9 cycles each. SCLK Table 2-2. Performance of DMA Access to External Memory Source Destination Approximate SCLKs For n Words...
Page 103: Memory
3 MEMORY This chapter discusses memory population specific to the ADSP-BF534, ADSP-BF536, and ADSP-BF537 processors. Functional memory archi- tecture is described in the ADSP-BF53x/BF56x Blackfin Processor Programming Reference. Memory Architecture Figure 3-1 on page 3-3 provides an overview of the ADSP-BF534 proces- sor system memory map.
Page 104: L1 Data Sram
Memory Architecture Table 3-1. Memory Configurations Type of Memory ADSP-BF534 ADSP-BF536 ADSP-BF537 Instruction SRAM/Cache, lockable 16K byte 16K byte 16K byte by Way or line Instruction SRAM 48K byte 48K byte 48K byte Data SRAM/Cache 32K byte 16K byte 32K byte Data SRAM 32K byte 16K byte...
Page 105 Memory ADSP-BF534 MEMORY MAP 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0000 RESERVED INTERNAL 0xFFA0 C000 MEMORY INSTRUCTION BANK B SRAM (16K BYTE)
Page 106 Memory Architecture ADSP-BF536 MEMORY MAP 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0000 RESERVED INTERNAL 0xFFA0 C000 MEMORY...
Page 107 Memory ADSP-BF537 MEMORY MAP 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0000 RESERVED INTERNAL 0xFFA0 C000 MEMORY INSTRUCTION BANK B SRAM (16K BYTE)
Page 108 L1 Instruction SRAM Table 3-2 lists the memory start locations of the L1 instruction memory subbanks. Table 3-2. L1 Instruction Memory Subbanks Memory Subbank Memory Start Location ADSP-BF534, ADSP-BF536, ADSP-BF537 0xFFA0 0000 0xFFA0 1000 0xFFA0 2000 0xFFA0 3000 0xFFA0 4000 0xFFA0 5000 0xFFA0 6000 0xFFA0 7000...
Page 109 Memory L1 Data SRAM Table 3-3 shows how the subbank organization is mapped into memory. Table 3-3. L1 Data Memory SRAM Subbank Start Addresses Memory Bank and Subbank ADSP-BF534 and ADSP-BF536 ADSP-BF537 Data Bank A, Subbank 0 0xFF80 0000 Data Bank A, Subbank 1 0xFF80 1000 Data Bank A, Subbank 2 0xFF80 2000...
Page 110: L1 Data Cache
L1 Data Cache L1 Data Cache When data cache is enabled (controlled by bits in the DMC[1:0] register), either 16K byte of data bank A or 16K byte of DMEM_CONTROL both data bank A and data bank B can be set to serve as cache. For the ADSP-BF534 and ADSP-BF537, the upper 16K byte is used.
Page 111: Dmem_Control Register
Memory DMEM_CONTROL Register The data memory control register ( ), shown in Figure 3-4, DMEM_CONTROL contains control bits for the L1 data memory. Data Memory Control Register (DMEM_CONTROL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFE0 0004 Reset = 0x0000 1001 15 14 13 12 11 10...
Page 112: Dtest_Command Register
Processor-Specific MMRs DTEST_COMMAND Register When the data test command register ( ) is written to, the DTEST_COMMAND L1 cache data or tag arrays are accessed, and the data is transferred through the data test data registers ( ). This register is DTEST DATA[1:0] shown in Figure...
Page 113: System Interrupts
4 SYSTEM INTERRUPTS This chapter discusses the System Interrupt Controller (SIC), which is specific to the ADSP-BF534, ADSP-BF536, ADSP-BF537 derivatives. While this chapter does refer to features of the Core Event Controller (CEC), it does not cover all aspects of it. Please refer to the ADSP-BF53x/BF56x Blackfin Processor Programming Reference for more information on the CEC.
Page 114: Interfaces
Interfaces Interfaces Figure 4-1 provides an overview of how the individual peripheral inter- rupt request lines connect to the SIC. It also shows how the four interrupt assignment registers ( ) control the assignment to the nine avail- SIC_IARx able peripheral request inputs of the CEC. The memory-mapped , and registers are part of...
Page 115 System Interrupts IPEND IMASK DMA ERROR ILAT DMAR0 BLOCK DONE DMAR1 BLOCK DONE DMAR0 OVERFLOW DMAR1 OVERFLOW PLL WAKEUP CAN ERROR MAC ERROR SPORT0 ERROR DMA0 (PPI) SPORT1 ERROR DMA3 (SPORT0 RX) PPI ERROR DMA4 (SPORT0 TX) SPI ERROR DMA5 (SPORT1 RX) UART0 ERROR UART1 ERROR DMA6 (SPORT1 RX)
Page 116 Description of Operation An interrupt is an event that changes the normal processor instruction flow and is asynchronous to program flow. In contrast, an exception is a software initiated event whose effects are synchronous to program flow. The event system is nested and prioritized. Consequently, several service routines may be active at any time, and a low priority event may be pre-empted by one of higher priority.
Page 117 System Interrupts Table 4-1. System and Core Event Mapping (Cont’d) Event Source Core Event Name System interrupts PLL wakeup interrupt IVG7 DMA error (generic) DMAR0 block done DMAR1 block done DMAR0 overflow DMAR1 overflow CAN error interrupt MAC error interrupt PPI error interrupt SPORT0 error interrupt SPORT1 error interrupt...
Page 118 Description of Operation Table 4-1. System and Core Event Mapping (Cont’d) Event Source Core Event Name System interrupts, continued DMA9 interrupt (UART0 TX) IVG10 TWI interrupt DMA7 interrupt (SPI) DMA8 interrupt (UART0 RX) DMA10 interrupt (UART1 RX) DMA11 interrupt (UART1 TX) Port H interrupt A IVG11 CAN RX interrupt...
Page 119: System Peripheral Interrupts
System Interrupts System Peripheral Interrupts To service the rich set of peripherals, the SIC has 32 interrupt request inputs and 9 interrupt request outputs which go to the CEC. The primary function of the SIC is to mask, group, and prioritize interrupt requests and to forward them to the 9 general-purpose interrupt inputs of the CEC –...
Page 120 Description of Operation of whether the particular interrupt is enabled at the peripheral itself. At reset, the contents of are all 0s to mask off all peripheral inter- SIC_IMASK rupts. Turning off a system interrupt mask and enabling the particular interrupt is performed by writing a 1 to a bit location in SIC_IMASK The SIC includes a read-only system interrupt status register (...
Page 121 System Interrupts register is not affected by the state of the system interrupt SIC_ISR mask register ( ) and can be read at any time. Writes to the SIC_IMASK register have no effect on its contents. SIC_ISR Peripheral DMA channels are mapped in a fixed manner to the peripheral interrupt IDs.
Page 122 Description of Operation read from or written to at any time. To prevent spurious or lost interrupt activity, this register should be written to only when all peripheral inter- rupts are disabled. The wakeup function is independent of the interrupt mask func- tion.
Page 123 System Interrupts Table 4-2 shows the peripheral interrupt events, the default mapping of each event, the peripheral interrupt ID used in the system interrupt assignment registers ( ), and the core interrupt ID. See SIC_IARx “SIC_IARx Registers” on page 4-18. Table 4-2.
Page 124 Description of Operation Table 4-2. System Interrupt Controller (SIC) (Cont’d) Peripheral Interrupt Default DMA Source Peripheral Default Default Event Mapping Interrupt ID Mapping Core Interrupt ID DMA channel 6 SPORT 1 TX IVG9 IVG10 IVG10 DMA channel 7 IVG10 DMA channel 8 UART0 RX IVG10 DMA channel 9...
Page 125 System Interrupts Table 4-2. System Interrupt Controller (SIC) (Cont’d) Peripheral Interrupt Default DMA Source Peripheral Default Default Event Mapping Interrupt ID Mapping Core Interrupt ID Port H interrupt B IVG11 Timer 0 IVG12 Timer 1 IVG12 Timer 2 IVG12 Timer 3 IVG12 Timer 4 IVG12...
Page 126: Programming Model
Programming Model Programming Model The programming model for the system interrupts is described in the fol- lowing sections. System Interrupt Initialization If the default assignments shown in Table 4-2 on page 4-11 are accept- able, then interrupt initialization involves only: •...
Page 127 System Interrupts 4. The registers, which map the peripheral interrupts to a SIC_IARx smaller set of general-purpose core interrupts ( IVG7 – IVG15 determine the core priority of interrupt A. adds interrupt A to its log of interrupts latched by the core ILAT but not yet actively being serviced.
Page 128: System Interrupt Controller Registers
System Interrupt Controller Registers RESET "INTERRUPT IVTMR A" IVHW PERIPHERAL CORE INTERRUPT CORE SYSTEM ASSIGN EVENT CORE REQUESTS INTERRUPT INTERRUPT SYSTEM VECTOR STATUS MASK MASK PRIORITY TABLE (ILAT) (IMASK) (SIC_IMASK) (SIC_IAR0..3) (EVT[15:0]) SYSTEM SYSTEM CORE WAKEUP STATUS PENDING (SIC_IWR) (SIC_ISR) (IPEND) TO DYNAMIC POWER MANAGEMENT...
Page 129 System Interrupts Table 4-3 defines the value to write in to configure a peripheral SIC_IARx for a particular IVG priority. Table 4-3. IVG Select Definitions General-purpose Interrupt Value in SIC_IAR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15 ADSP-BF537 Blackfin Processor Hardware Reference 4-17...
Page 130: Sic_Iarx Registers
System Interrupt Controller Registers SIC_IARx Registers System Interrupt Assignment Register 0 (SIC_IAR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0110 Reset = 0x2221 1000 DMA Channel 0 (PPI) DMA Channel 5 Interrupt (SPORT1 RX) Interrupt DMA Channel 3 (SPORT0...
Page 131 System Interrupts System Interrupt Assignment Register 2 (SIC_IAR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x5555 5444 0xFFC0 0118 Timer 4 Interrupt Timer 1 Interrupt Timer 3 Interrupt Timer 2 Interrupt 15 14 13 12 11 10 Timer 0 Interrupt CAN TX Interrupt...
Page 132: Sic_Imask Register
System Interrupt Controller Registers SIC_IMASK Register System Interrupt Mask Register (SIC_IMASK) For all bits, 0 - Interrupt masked, 1 - Interrupt enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 010C Reset = 0x0000 0000 Software Watchdog CAN TX Interrupt...
Page 133: Sic_Isr Register
System Interrupts SIC_ISR Register System Interrupt Status Register (SIC_ISR) For all bits, 0 - Deasserted, 1 - Asserted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0120 Reset = 0x0000 0000 Software Watchdog CAN TX Interrupt Timer, Port F Inter-...
Page 134: Sic_Iwr Register
System Interrupt Controller Registers SIC_IWR Register System Interrupt Wakeup-enable Register (SIC_IWR) For all bits, 0 - Wakeup function not enabled, 1 - Wakeup function enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0124 Reset = 0xFFFF FFFF Software Watchdog...
Page 135: Programming Examples
System Interrupts Programming Examples The following sections provide examples for programming system interrupts. Clearing Interrupt Requests When the processor services a core event it automatically clears the requesting bit in the register and no further action is required by the ILAT interrupt service routine.
Page 136 Programming Examples Listing 4-1. Servicing GPIO Interrupt Request #include <defBF537.h> .section program; _portg_a_isr: /* push used registers */ [--sp] = (r7:7, p5:5); /* clear interrupt request on GPIO pin PG2 */ /* no matter whether used A or B channel */ p5.l = lo(PORTGIO_CLEAR);...
Page 137 System Interrupts of the service routine, or the instruction is followed by another set SSYNC of instructions before the service routine returns. Commonly, a pop-mul- tiple instruction is used for this purpose as shown in Listing 4-1. The level-sensitive nature of peripheral interrupts enables more than one of them to share the same IVG channel and therefore the same interrupt priority.
Page 138 Programming Examples 4-26 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 139: Direct Memory Access
5 DIRECT MEMORY ACCESS This chapter describes the Direct Memory Access (DMA) controller. Fol- lowing an overview and list of key features is a description of operation and functional modes of operation. The chapter concludes with a pro- gramming model, consolidated register definitions, and programming examples.
Page 140 Overview and Features The DMA controller can perform several types of data transfers: • Peripheral DMA transfers data between memory and on-chip peripherals. The processor has 12 peripheral DMA channels that support 7 peripherals. • Ethernet MAC (dedicated DMA channel for transmit and receive.
Page 141 Direct Memory Access set of parameters stored within memory to initiate a DMA sequence. This sort of transfer allows the chaining together of multiple DMA sequences. In descriptor-based DMA operations, a DMA channel can be pro- grammed to automatically set up and start another DMA transfer after the current sequence completes.
Page 142 Overview and Features • SPORT0 receive • SPORT0 transmit • SPORT1 receive • SPORT1 transmit • SPI receive/transmit • UART0 receive • UART0 transmit • UART1 receive • UART1 transmit • MDMA0 destination • MDMA0 source • MDMA1 destination • MDMA1 source ADSP-BF537 Blackfin Processor Hardware Reference...
Page 143: Dma Controller Overview
Direct Memory Access DMA Controller Overview Figure 5-1 provides a block diagram of the DMA controller. DMAR0 DMAR1 CCLK SCLK DMA TRAFFIC CONTROL IRQ 1 MDMA 0 SOURCE CONTROL FIFO IRQ 29 MDMA 0 DESTINATION CONTROL HMDMA 0 MDMA 1 SOURCE CONTROL FIFO IRQ 30 HMDMA 1...
Page 144: External Interfaces
DMA Controller Overview External Interfaces The DMA does not connect external memories and devices directly. Rather, data is passed through the EBIU port. Any kind of device that is supported by the EBIU can also be accessed by peripheral DMA or mem- ory DMA operation.
Page 145: Peripheral Dma
Direct Memory Access The 16-bit DMA Access Bus (DAB) connects the DMA controller to the on-chip peripherals, PPI, SPI, Ethernet MAC, the SPORTs, and the UARTs. It operates at frequency. SCLK The 16-bit DMA External Bus (DEB) connects the DMA controller to the EBIU port.
Page 146 DMA Controller Overview Table 5-1. Default Mapping of Peripheral to DMA (Cont’d) DMA Channel PMAP Default Value Peripheral Mapped by Default DMA 2 Ethernet MAC transmit DMA 3 SPORT0 receive DMA 4 SPORT0 transmit DMA 5 SPORT1 receive DMA 6 SPORT1 transmit DMA 7 DMA 8...
Page 147: Memory Dma
Direct Memory Access channel, that channel is disabled—DMA requests are ignored, and no DMA grants are issued. The DMA requests are also not for- warded from the peripheral to the interrupt controller. The twelve peripheral DMA channels work completely independently from each other.
Page 148 DMA Controller Overview A memory-to-memory transfer always requires the source and the destina- tion channel to be enabled. The four channels are hardwired for DMA priorities 12 through 15. Each source/destination channel forms a “stream,” and these two streams are hardwired for DMA priorities 8 through 11.
Page 149: Handshaked Memory Dma Mode
Direct Memory Access To start an MDMA transfer operation, the MMRs for the source and des- tination channels are written, each in a manner similar to peripheral DMA. Note the register for the source channel must be writ- DMAx_CONFIG ten before the register for the destination channel.
Page 150: Modes Of Operation
Modes of Operation Modes of Operation The following sections describe the DMA operation. Register-based DMA Operation Register-based DMA is the traditional kind of DMA operation. Software writes source or destination address and length of the data to be trans- ferred into memory-mapped registers and then starts DMA operation. For basic operation the software performs these steps: •...
Page 151: Stop Mode
Direct Memory Access • Write the operation mode to the register. These bits DMAx_CONFIG in particular need to be changed as needed: • The bit enables the DMA channel. DMAEN • The bit controls the DMA direction. DMAs that read from memory keep this bit cleared, for example, transmit- ting peripheral DMAs and the source channel of memory DMAs.
Page 152: Autobuffer Mode
Modes of Operation should clear the enable bit to disable a paused channel. Stop mode DMAEN is entered if the bit field in the DMA channel’s register FLOW DMAx_CONFIG is 0. The field must always be 0 in this mode. NDSIZE For receive (memory write) operation, the bit functions almost...
Page 153: Examples Of Two-Dimensional Dma
Direct Memory Access value is the byte-address increment that is applied DMAx_X_MODIFY after each transfer that decrements the register. The DMAx_CURR_X_COUNT value is not applied when the inner loop count is ended by DMAx_X_MODIFY decrementing from 1 to 0, except that it is applied on DMAx_CURR_X_COUNT the final transfer when is 1 and...
Page 154: Descriptor-Based Dma Operation
Modes of Operation This produces the following address offsets from the start address: 0,1,2,...15, N,N + 1, ... N + 15, 2N, 2N + 1,... 2N + 15, ... 7N, 7N + 1,... 7N + 15, Example 2: Receive a video datastream of bytes, (R,G,B pixels) ×...
Page 155: Descriptor List Mode
Direct Memory Access A descriptor describes what kind of operation should be performed next by the DMA channel. This includes the DMA configuration word as well as data source/destination address, transfer count, and address modify val- ues. A DMA sequence controlled by one descriptor is called a work unit. Optionally, an interrupt can be requested at the end of any work unit by setting the bit in the configuration word of the respective...
Page 156: Descriptor Array Mode
Modes of Operation descriptor must reside in the same 64 KB address space as the first one, because the upper 16 bits of the register are not DMAx_NEXT_DESC_PTR updated. Descriptor list modes are started by writing first to the DMAx_NEXT_DESC_ register and then to the register.
Page 157: Mixing Flow Modes
Direct Memory Access All the other registers not loaded from the descriptor retain their prior val- ues, although the , and DMAx_CURR_ADDR DMAx_CURR_X_COUNT DMAx_CURR_Y_ registers are reloaded between the descriptor fetch and the start of COUNT DMA operation. Table 5-2 shows the offsets for descriptor elements in the three modes described above.
Page 158: Functional Description
Functional Description the first descriptor if a descriptor array is used in an endless manner. If the descriptor chain is not endless and the DMA is required to stop after a cer- tain descriptor has been processed, the last descriptor is typically processed in stop mode, that is, its fields are 0, but its bit is...
Page 159 Direct Memory Access descriptor elements in memory. After the descriptor fetch, if any, is com- pleted, DMA operation begins, initiated by writing with DMAx_CONFIG DMAEN = 1 USER WRITES SOME OR ALL DMA PARAMETER REGISTERS, AND THEN WRITES DMA_CONFIG BAD DMA_CONFIG? DMA ERROR DMAEN = 0 TEST DMAEN...
Page 160 Functional Description NDSIZE = 0 OR NDSIZE > MAX_SIZE* TEST NDSIZE ABORT OCCURS NDSIZE > 0 AND NDSIZE <= MAX_SIZE* READ NDSIZE ELEMENTS OF DESCRIPTOR INTO PARAMETER REGISTERS VIA CURRENT DESCRIPTOR POINTER FLOW = 0 OR 1 CLEAR DFETCH IN IRQ_STATUS DMA TRANSFER BEGINS AND...
Page 161 Direct Memory Access When is written directly by software, the DMA controller DMAx_CONFIG recognizes this as the special startup condition that occurs when starting DMA for the first time on this channel or after the engine has been stopped ( FLOW = 0 When the descriptor fetch is complete and , the...
Page 162 Functional Description is not part of the descriptor, the previous settings DMACFG DMAx_CONFIG (as written by MMR access at startup) control the work unit operation. If is part of the descriptor, then the value programmed DMACFG DMAx_CONFIG by the MMR access controls only the loading of the first descriptor from memory.
Page 163: Dma Refresh
Direct Memory Access Then DMA data transfer operation begins, as shown in Figure 5-3 on page 5-22. DMA Refresh On completion of a work unit, the DMA controller: • Completes the transfer of all data between memory and the DMA unit.
Page 164 Functional Description Next, fetches a descriptor from memory into DMA registers via the new contents of , while incrementing DMAx_CURR_DESC_PTR DMAx_ . The first descriptor element loaded is a new 16-bit CURR_DESC_PTR value for the lower 16 bits of , followed by the DMAx_NEXT_DESC_PTR rest of the descriptor elements.
Page 165: Work Unit Transitions
Direct Memory Access • If (descriptor array, descriptor list small, or FLOW 4, 6, or 7 descriptor list large, respectively) the DMA controller clears the bit in the register. DFETCH DMAx_IRQ_STATUS • If = any value but 0 (Stop), the DMA controller begins the FLOW next work unit, contending with other channels for priority on the memory buses.
Page 166: Dma Transmit And Mdma Source
Functional Description the cost of higher latency in the transition. In synchronized transitions, the DMA FIFO pipeline is drained to the destination or flushed (RX data discarded) between work units. Work unit transitions for MDMA streams are controlled by the bit of the MDMA source channel’s register.
Page 167 Direct Memory Access however, and not yet at the peripheral, so the DMA interrupt should not be used as the sole means of synchronizing the shutdown or reconfigura- tion of the peripheral following a transmission. (continuous transition) on a transmit (memory read) SYNC = 0 descriptor, the next descriptor is required to have the same data word size, read/write direction, and source memory (internal vs.
Page 168: Dma Receive
Functional Description DMA Receive In DMA receive (memory write) channels, the bit controls the han- SYNC dling of the DMA FIFO between descriptor chains (not individual descriptors), when the DMA channel is paused. The DMA channel pauses after descriptors with mode, and may be restarted (for exam- FLOW = STOP ple, after an interrupt) by writing the channel’s...
Page 169: Stopping Dma Transfers
Direct Memory Access If a descriptor chain begins with a bit of 1, there is no restriction on SYNC DMA word size of the new chain in comparison to the previous chain. The DMA word size must not change between one descriptor and the next in any DMA receive (memory write) channel within a sin- gle descriptor chain, regardless of the bit setting.
Page 170: Dma Errors (Aborts)
Functional Description a row in its usage of the relevant memory space to allow up to three pending DMA accesses to issue, plus allowing enough memory access time for the accesses themselves to complete. DMA Errors (Aborts) The DMA controller flags conditions that cause the DMA process to end abnormally (that is, abort).
Page 171 Direct Memory Access • A disallowed register write occurred while the channel was run- ning. Only the registers can be DMAx_CONFIG DMAx_IRQ_STATUS written when DMA_RUN = 1 • An address alignment error occurred during any memory access. For example, register (16 bit) but the DMAx_CONFIG WDSIZE = 1...
Page 172: Dma Control Commands
Functional Description • Descriptor chain indicates data buffers that are not in the same internal/external memory space. • In 2D DMA, X_COUNT = 1 Table 5-3. Legal NDSIZE Values FLOW NDSIZE Note 0 < NDSIZE <= 7 Descriptor array, no descriptor pointer fetched 0 <...
Page 173 Direct Memory Access restrictions regarding work units and descriptor chains (described later in this section) so that the peripheral operates properly whenever it issues DMA control commands. The ADSP-BF536/ADSP-BF537 processors have just one DMA-manage- ment-capable peripheral, the Ethernet MAC. Refer to Chapter 8, “Ethernet MAC”, for a description of how receive and transmit channels...
Page 174 Functional Description Additional information for the control commands includes: • Restart The restart control command causes the current work unit to inter- rupt processing and start over, using the addresses and counts from , and . No interrupt DMAx_START_ADDR DMAx_X_COUNT DMAx_Y_COUNT is signalled.
Page 175 Direct Memory Access stream into work units on its own, perhaps as a result of parsing the data currently passing though its supported communication chan- nel, without direct real-time control by the processor. If a channel programmed for transmit (memory read) receives a finish control command, the channel momentarily pauses while any pending memory reads initiated prior to the finish command are completed.
Page 176: Restrictions
Functional Description • Request Data Urgent The request data urgent control command behaves identically to the DMA request control command, except that while it is asserted the DMA channel performs its memory accesses with urgent prior- ity. This includes both data and descriptor-fetch memory accesses. A DMA-management-capable peripheral might use this control command if an internal FIFO is approaching a critical condition, for example.
Page 177: Receive Restart Or Finish
Direct Memory Access Receive Restart or Finish No restart or finish control command may be issued by a peripheral to a channel configured for memory write unless either (a) the peripheral has already performed at least five DMA transfers in the current work unit, or (b) the previous work unit was terminated by a finish control command and the peripheral has performed at least one DMA transfer in the current work unit.
Page 178: Handshaked Memory Dma Operation
Functional Description Handshaked Memory DMA Operation Both inputs have their own set of control and status registers. DMARx Handshake operation for MDMA0 is enabled by the bit in the HMDMAEN register. Similarly, the bit in the HMDMA0_CONTROL HMDMAEN HMDMA1_CONTROL register enables handshake mode for MDMA1. It is important to understand that the handshake hardware works com- pletely independent from the descriptor and autobuffer capabilities of the MDMA, allowing most flexible combinations of logical data organization...
Page 179: Pipelining Dma Requests
Direct Memory Access Since the block count registers are 16 bits wide, blocks can group up to 65535 transfers. Once a block transfer has been started, the registers return HMDMAx_BCOUNT the remaining number of transfers to complete the current block. When the complete block has been processed, the register returns HMDMAx_BCOUNT...
Page 180 Functional Description Figure 5-4 illustrates how an asynchronous FIFO could be connected. In such a scenario the bit was cleared to let the request pin listen to DMARx falling edges. The Blackfin processor does not evaluate the full flag such FIFOs usually provide, because asynchronous polling of that signal would reduce the system throughput drastically.
Page 181: Hmdma Interrupts
Direct Memory Access half the FIFO depth. Then, the MDMA does not start consuming data as long as the FIFO is not half filled. BLACKFIN 1024K x 16 FIFO O0 .. O15 I0 .. I15 D0 .. D15 AMSx DMARx Figure 5-5.
Page 182: Dma Performance
Functional Description The block done interrupt signals that a complete MDMA block as defined by the register has been transferred, that is, when the HMDMAx_BCINIT register decrements to zero. While the bit enables this HMDMAx_BCOUNT BDIE interrupt, the bit can gate it until the edge count also becomes zero, MBDI meaning that all requested MDMA transfers have been completed.
Page 183: Dma Throughput
Direct Memory Access • How often do competing DMA channels require the bus systems to alter direction? • How often do competing DMA or core accesses cause the SDRAM to open different pages? • Is there a way to distribute DMA requests nicely over time? A key feature of the DMA architecture is the separation of the activity on the peripheral DMA bus (the DMA Access Bus (DAB)) from the activity on the buses between the DMA and memory (the DMA Core Bus (DCB)
Page 184 Functional Description When all DMA channels’ traffic is taken in the aggregate: • Transfers between the peripherals and the DMA unit have a maxi- mum rate of one 16-bit transfer per system clock. • Transfers between the DMA unit and internal memory (L1) have a maximum rate of one 16-bit transfer per system clock.
Page 185 Direct Memory Access • Descriptor fetches consume one DMA memory cycle per 16-bit word read from memory, but do not delay transfers on the DAB bus. • Initialization of a DMA channel stalls DMA activity for one cycle. This occurs when changes from 0 to 1 or when the DMAEN SYNC...
Page 186: Memory Dma Timing Details
Functional Description Memory DMA Timing Details When the destination register is written, MDMA operation DMAx_CONFIG starts, after a latency of 3 cycles. SCLK First, if either MDMA channel has been selected to use descriptors, the descriptors are fetched from memory. The destination channel descriptors are fetched first.
Page 187 Direct Memory Access Table 5-5. Priority and Default Mapping of Peripheral to DMA Priority DMA Channel PMAP Default Peripheral Mapped by Default Value Highest DMA 0 PPI receive or transmit DMA 1 Ethernet MAC receive DMA 2 Ethernet MAC transmit DMA 3 SPORT0 receive DMA 4...
Page 188: Temporary Dma Urgency
Functional Description Temporary DMA Urgency Typically, DMA transfers for a given peripheral occur at regular intervals. Generally, the shorter the interval, the higher the priority that should be assigned to the peripheral. If the average bandwidth of all the peripherals is not too large a fraction of the total, then all peripherals’...
Page 189: Memory Dma Priority And Scheduling
Direct Memory Access DMA requests from an MDMA channel become urgent when handshaked operation is enabled and the DMARx edge count exceeds the value stored in the register. If handshaked operation is disabled, soft- HMDMAx_ECURGENT ware can control urgency of requests directly by altering the bit field in the register.
Page 190 Functional Description If two MDMA streams are used (S0-D0 and S1-D1), the user may choose to allocate bandwidth either by fixed stream priority or by a round robin scheme. This is selected by programming the MDMA_ROUND_ROBIN_PERIOD field in the register (see “Static Channel Prioritization”...
Page 191: Traffic Control
Direct Memory Access transfer corresponding to a count of 1, the MDMA stream selection is passed automatically to the other stream with zero overhead, and the counter is reloaded with the period value from MDMA_ROUND_ROBIN_COUNT . In this cycle, if the other MDMA stream is MDMA_ROUND_ROBIN_PERIOD ready to perform a transfer, the stream selection is locked on the new MDMA stream.
Page 192 Functional Description is requesting DMA but its FIFO is not ready (for example, an empty transmit FIFO or full receive FIFO). For more information, see “Tempo- rary DMA Urgency” on page 5-50. Traffic control is an important consideration in optimizing use of DMA resources.
Page 193: Programming Model
Direct Memory Access This type of traffic control represents a trade-off of latency to improve uti- lization (efficiency). Higher traffic timeouts might increase the length of time each request waits for its grant, but it often dramatically improves the maximum attainable bandwidth in congested systems, often to above 90%.
Page 194: Synchronization Of Software And Dma
Programming Model Synchronization of Software and DMA A critical element of software DMA management is synchronization of DMA buffer completion with the software. This can best be done using interrupts, polling of , or a combination of both. Polling DMAx_IRQ_STATUS for address or count can only provide synchronization within loose toler- ances comparable to pipeline lengths.
Page 195 Direct Memory Access Polling of the current address, pointer, and count registers can permit loose synchronization of DMA with software, however, if allowances are made for the lengths of the DMA/memory pipeline. The length of the DMA FIFO for a peripheral DMA channel is four locations (either four 8- or 16-bit data elements, or two 32-bit data elements) and for an MDMA FIFO is eight locations (four 32-bit data elements).
Page 196: Single-Buffer Dma Transfers
Programming Model read DMA, the final memory read data will have been safely received in the DMA’s FIFO; for memory write DMA, the DMA unit will have received an acknowledge from L1 memory or the EBIU that the data has been written.
Page 197 Direct Memory Access transfer, which might overwrite or re-read the first buffer location before it is processed by software. This scheme may be workable if the system design guarantees that the data repeat period is longer than the interrupt latency under all circumstances. •...
Page 198: Descriptor Structures
Programming Model for four sub-buffers DMAx_Y_COUNT = 4 , same as for contiguous DMAx_Y_MODIFY = 4 DMAx_X_MODIFY sub-buffers The synchronization core might read to determine DMAx_Y_COUNT which sub-buffer is currently being transferred, and then allow one full sub-buffer to account for pipelining. For example, if a read of shows a value of 3, then the software should assume DMAx_Y_COUNT that sub-buffer 3 is being transferred, but some portion of...
Page 199: Descriptor Queue Management
Direct Memory Access It is important to remember the meaning of the various fields in the descriptor elements when building a list or array of DMA DMAx_CONFIG descriptors. In particular: • The lower byte of specifies the DMA transfer to be DMAx_CONFIG performed by the current descriptor (for example, interrupt-enable, 2D mode)
Page 200: Descriptor Queue Using Interrupts On Every Descriptor
Programming Model structure. In this case, the members of each descriptor NDPH NDPL could even be written once at startup, and skipped over as each descrip- tor’s new contents are written. The recommended method for synchronization of a descriptor queue is through the use of an interrupt.
Page 201: Descriptor Queue Using Minimal Interrupts
Direct Memory Access If the counts are unequal, the software instead modifies the next-to-last descriptor’s value so that its upper half ( DMAx_CONFIG FLOW NDSIZE now describes the newly queued descriptor. This operation does not dis- rupt the DMA channel, provided the rest of the descriptor data structure is initialized in advance.
Page 202 Programming Model When each new DMA request is processed, the software’s non-interrupt code fills in a new descriptor’s contents and adds it to the waiting portion of the queue. The descriptor’s word should have a value DMAx_CONFIG FLOW of zero. If more than one request is received before the DMA queue com- pletion interrupt occurs, the non-interrupt code should queue later descriptors, forming a waiting portion of the queue that is disconnected from the active portion of the queue being processed by the DMA unit.
Page 203: Software Triggered Descriptor Fetches
Direct Memory Access active queue. The interrupt handler should then pass a message back to the non-interrupt software indicating the location of the last descriptor accepted into the active queue. If, on the other hand, the interrupt han- dler reads its mailbox and finds a value of zero, indicating DMAx_CONFIG there is no more work to perform, then it should pass an appropriate mes-...
Page 204 Programming Model The next descriptor pointer remains valid, if the DMA halts and is restarted. As soon as the bit clears, software can restart the DMA DMA_RUN and force the DMA controller to fetch the next descriptor. To accomplish this, the software writes a value with the bit set and with proper val- DMAEN ues in the...
Page 205: Dma Registers
Direct Memory Access If all fields in a descriptor chain have the fields set DMACFG FLOW NDSIZE to zero, the individual DMA sequences do not start until triggered by soft- ware. This is useful when the DMAs need to be synchronized with other events in the system, and it is typically performed by interrupt service rou- tines.
Page 206: Dma Channel Registers
DMA Registers DMA Channel Registers The processor features twelve peripheral DMA channels and two channel pairs for memory DMA. All channels have an identical set of registers summarized in Table 5-6. Table 5-6 lists the generic names of the DMA registers. For each register, the table also shows the MMR offset, a brief description of the register, the register category.
Page 207 Direct Memory Access Table 5-6. Generic Names of the DMA Memory-mapped Registers (Cont’d) Generic MMR Name MMR Description Register Name of Offset Category Corresponding Descriptor Element in Memory 0x20 CURR_DESC_PTR Current Descriptor Pointer Current 0x24 CURR_ADDR Current DMA Address Current 0x28 IRQ_STATUS Interrupt Status register:...
Page 208 DMA Registers “yy” stands for either “D0”, “S0”, “D1”, or “S1” to indicate destination and source channel registers of MDMA0 and MDMA1. For example, the configuration register of peripheral DMA channel 6 is called DMA6_CONFIG The one for MDMA1 source channel is called MDMA_S1_CONFIG The generic MMR names shown in Table 5-6...
Page 209: Dmax_Peripheral_Map
Direct Memory Access DMAx_PERIPHERAL_MAP/MDMA_yy_PERIPHERAL_MAP Registers Each DMA channel’s peripheral map register ( DMAx_PERIPHERAL_ , shown in Figure 5-6) contains bits that: MAP/MDMA_yy_PERIPHERAL_MAP • Map the channel to a specific peripheral. • Identify whether the channel is a peripheral DMA channel or a memory DMA channel.
Page 210 DMA Registers Table 5-7. Peripheral Map Register Memory-mapped Addresses Register Name Memory-mapped Address DMA0_PERIPHERAL_MAP 0xFFC0 0C2C DMA1_PERIPHERAL_MAP 0xFFC0 0C6C DMA2_PERIPHERAL_MAP 0xFFC0 0CAC DMA3_PERIPHERAL_MAP 0xFFC0 0CEC DMA4_PERIPHERAL_MAP 0xFFC0 0D2C DMA5_PERIPHERAL_MAP 0xFFC0 0D6C DMA6_PERIPHERAL_MAP 0xFFC0 0DAC DMA7_PERIPHERAL_MAP 0xFFC0 0DEC DMA8_PERIPHERAL_MAP 0xFFC0 0E2C DMA9_PERIPHERAL_MAP 0xFFC0 0E6C DMA10_PERIPHERAL_MAP...
Page 211 Direct Memory Access Table 5-8 lists the binary peripheral map settings for each DMA-capable peripheral. Table 5-8. Peripheral Mapping Default Peripheral Default PERIPHERAL_ Comments Channel Mapping MAP Setting (Binary) DMA0 PPI receive/transmit b#0000 0000 0000 0000 (highest priority) DMA1 Ethernet receive b#0001 0000 0000 0000 Invalid PMAP default setting on...
Page 212: Dmax_Config/Mdma_Yy_Config Registers
DMA Registers DMAx_CONFIG/MDMA_yy_CONFIG Registers The DMA configuration register ( , shown DMAx_CONFIG/MDMA_yy_CONFIG) Figure 5-7, is used to set up DMA parameters and operating modes. Note that writing the register while DMA is already running DMAx_CONFIG will cause a DMA error unless writing with the bit set to 0.
Page 213 Direct Memory Access Table 5-9. Configuration Register Memory-mapped Addresses Register Name Memory-mapped Address DMA0_CONFIG 0xFFC0 0C08 DMA1_CONFIG 0xFFC0 0C48 DMA2_CONFIG 0xFFC0 0C88 DMA3_CONFIG 0xFFC0 0CC8 DMA4_CONFIG 0xFFC0 0D08 DMA5_CONFIG 0xFFC0 0D48 DMA6_CONFIG 0xFFC0 0D88 DMA7_CONFIG 0xFFC0 0DC8 DMA8_CONFIG 0xFFC0 0E08 DMA9_CONFIG 0xFFC0 0E48 DMA10_CONFIG...
Page 214 DMA Registers interrupts are still filtered out by the DMA unit. The channel may be restarted simply by another write to the register DMAx_CONFIG specifying the next work unit, in which the bit is set to 1. DMAEN 0x1 - autobuffer mode. In this mode, no descriptors in memory are used.
Page 215 Direct Memory Access • (data interrupt enable). This bit specifies whether to allow DI_EN completion of a work unit to generate a data interrupt. • (data interrupt timing select). This bit specifies the timing DI_SEL of a data interrupt—after completing the whole buffer or after completing each row of the inner loop.
Page 216: Mdma_Yy_Irq_Status Registers
DMA Registers • (DMA direction). This bit specifies DMA direction—memory read (0) or memory write (1). • (DMA channel enable). This bit specifies whether to enable DMAEN a given DMA channel. When a peripheral DMA channel is enabled, interrupts from the peripheral denote DMA requests.
Page 217 Direct Memory Access For a memory write DMA channel, the state of the bit has DMA_RUN no meaning after the last event has been signaled. It does DMA_DONE not indicate the status of the DMA FIFO. For MDMA transfers where it is not desired to use an interrupt to notify when the DMA operation has ended, software should poll bit, and not the bit, to determine when the...
Page 218 DMA Registers Table 5-10. Interrupt Status Register Memory-mapped Addresses Register Name Memory-mapped Address DMA0_IRQ_STATUS 0xFFC0 0C28 DMA1_IRQ_STATUS 0xFFC0 0C68 DMA2_IRQ_STATUS 0xFFC0 0CA8 DMA3_IRQ_STATUS 0xFFC0 0CE8 DMA4_IRQ_STATUS 0xFFC0 0D28 DMA5_IRQ_STATUS 0xFFC0 0D68 DMA6_IRQ_STATUS 0xFFC0 0DA8 DMA7_IRQ_STATUS 0xFFC0 0DE8 DMA8_IRQ_STATUS 0xFFC0 0E28 DMA9_IRQ_STATUS 0xFFC0 0E68 DMA10_IRQ_STATUS...
Page 219 Direct Memory Access Separate interrupt request (IRQ) levels are allocated for data and periph- eral error interrupts, and DMA error interrupts. Table 5-11. Data Driven Interrupts Interrupt Name Description No Interrupt Interrupts can be disabled for a given work unit. Peripheral Interrupt These are peripheral (non-DMA) interrupts.
Page 220: Mdma_Yy_Start_Addr Registers
DMA Registers DMAx_START_ADDR/MDMA_yy_START_ADDR Registers The start address register ( ), shown DMAx_START_ADDR/MDMA_yy_START_ADDR Figure 5-9, contains the start address of the data buffer currently tar- geted for DMA. Start Address Registers (DMAx_START_ADDR/ MDMA_yy_START_ADDR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 For Memory-...
Page 221: Dmax_Curr_Addr/Mdma_Yy_Curr_Addr Registers
Direct Memory Access Table 5-12. Start Address Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address DMA8_START_ADDR 0xFFC0 0E04 DMA9_START_ADDR 0xFFC0 0E44 DMA10_START_ADDR 0xFFC0 0E84 DMA11_START_ADDR 0xFFC0 0EC4 MDMA_D0_START_ADDR 0xFFC0 0F04 MDMA_S0_START_ADDR 0xFFC0 0F44 MDMA_D1_START_ADDR 0xFFC0 0F84 MDMA_S1_START_ADDR 0xFFC0 0FC4 DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR Registers The current address register ( DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR shown in...
Page 222 DMA Registers Current Address Registers (DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) R/W prior to enabling channel; RO after enabling channel For Memory- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mapped Reset = Undefined addresses, see Table 5-13.
Page 223: Dmax_X_Count/Mdma_Yy_X_Count Registers
Direct Memory Access Table 5-13. Current Address Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address MDMA_D0_CURR_ADDR 0xFFC0 0F24 MDMA_S0_CURR_ADDR 0xFFC0 0F64 MDMA_D1_CURR_ADDR 0xFFC0 0FA4 MDMA_S1_CURR_ADDR 0xFFC0 0FE4 DMAx_X_COUNT/MDMA_yy_X_COUNT Registers For 2D DMA, the inner loop count register ( DMAx_X_COUNT/MDMA_yy_X_ ), shown in Figure 5-11, contains the inner loop count.
Page 224: Dmax_Curr_X_Count Mdma_Yy_Curr_X_Count Registers
DMA Registers Table 5-14. Inner Loop Count Register Memory-mapped Addresses Register Name Memory-mapped Address DMA0_X_COUNT 0xFFC0 0C10 DMA1_X_COUNT 0xFFC0 0C50 DMA2_X_COUNT 0xFFC0 0C90 DMA3_X_COUNT 0xFFC0 0CD0 DMA4_X_COUNT 0xFFC0 0D10 DMA5_X_COUNT 0xFFC0 0D50 DMA6_X_COUNT 0xFFC0 0D90 DMA7_X_COUNT 0xFFC0 0DD0 DMA8_X_COUNT 0xFFC0 0E10 DMA9_X_COUNT 0xFFC0 0E50 DMA10_X_COUNT...
Page 225 Direct Memory Access time an element is transferred. Expiration of the count in this register sig- nifies that DMA is complete. In 2D DMA, the DMAx_CURR_X_COUNT register value is 0 only when the entire transfer is complete. Between rows it is equal to the value of the register.
Page 226: Dmax_X_Modify Mdma_Yy_X_Modify Registers
DMA Registers Table 5-15. Current Inner Loop Count Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address DMA9_CURR_X_COUNT 0xFFC0 0E70 DMA10_CURR_X_COUNT 0xFFC0 0EB0 DMA11_CURR_X_COUNT 0xFFC0 0EF0 MDMA_D0_CURR_X_COUNT 0xFFC0 0F30 MDMA_S0_CURR_X_COUNT 0xFFC0 0F70 MDMA_D1_CURR_X_COUNT 0xFFC0 0FB0 MDMA_S1_CURR_X_COUNT 0xFFC0 0FF0 DMAx_X_MODIFY/MDMA_yy_X_MODIFY Registers The inner loop address increment register ( DMAx_X_MODIFY/MDMA_yy_X_ ), shown in Figure...
Page 227 Direct Memory Access field may be set to 0. In this case, DMA is performed DMAx_X_MODIFY repeatedly to or from the same address. This is useful, for example, in transferring data between a data register and an external memory-mapped peripheral. Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) R/W prior to enabling channel;...
Page 228: Mdma_Yy_Y_Count Registers
DMA Registers Table 5-16. Inner Loop Address Increment Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address DMA11_X_MODIFY 0xFFC0 0ED4 MDMA_D0_X_MODIFY 0xFFC0 0F14 MDMA_S0_X_MODIFY 0xFFC0 0F54 MDMA_D1_X_MODIFY 0xFFC0 0F94 MDMA_S1_X_MODIFY 0xFFC0 0FD4 DMAx_Y_COUNT/MDMA_yy_Y_COUNT Registers For 2D DMA, the outer loop count register ( DMAx_Y_COUNT/MDMA_yy_Y_ ), shown in Figure...
Page 229: Dmax_Curr_Y_Count Mdma_Yy_Curr_Y_Count Registers
Direct Memory Access Table 5-17. Outer Loop Count Register Memory-mapped Addresses Register Name Memory-mapped Address DMA0_Y_COUNT 0xFFC0 0C18 DMA1_Y_COUNT 0xFFC0 0C58 DMA2_Y_COUNT 0xFFC0 0C98 DMA3_Y_COUNT 0xFFC0 0CD8 DMA4_Y_COUNT 0xFFC0 0D18 DMA5_Y_COUNT 0xFFC0 0D58 DMA6_Y_COUNT 0xFFC0 0D98 DMA7_Y_COUNT 0xFFC0 0DD8 DMA8_Y_COUNT 0xFFC0 0E18 DMA9_Y_COUNT 0xFFC0 0E58...
Page 230 DMA Registers or 1 to 0 transition), signifying completion of an entire row DMAx_X_COUNT transfer. After a 2D DMA session is complete, DMAx_CURR_Y_COUNT = 1 DMAx_CURR_X_COUNT = 0 Current Outer Loop Count Registers (DMAx_CURR_Y_COUNT/ MDMA_yy_CURR_Y_COUNT) R/W prior to enabling channel; RO after enabling channel For Memory- 15 14 13 12 11 10 mapped...
Page 231: Dmax_Y_Modify/Mdma_Yy_Y_Modify Registers
Direct Memory Access Table 5-18. Current Outer Loop Count Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address DMA11_CURR_Y_COUNT 0xFFC0 0EF8 MDMA_D0_CURR_Y_COUNT 0xFFC0 0F38 MDMA_S0_CURR_Y_COUNT 0xFFC0 0F78 MDMA_D1_CURR_Y_COUNT 0xFFC0 0FB8 MDMA_S1_CURR_Y_COUNT 0xFFC0 0FF8 DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY Registers The outer loop address increment register ( DMAx_Y_MODIFY/MDMA_yy_Y_ ) contains a signed, two’s-complement value.
Page 232: Dmax_Next_Desc_Ptr Mdma_Yy_Next_Desc_Ptr Registers
DMA Registers Table 5-19. Outer Loop Address Increment Register Memory-mapped Addresses Register Name Memory-mapped Address DMA0_Y_MODIFY 0xFFC0 0C1C DMA1_Y_MODIFY 0xFFC0 0C5C DMA2_Y_MODIFY 0xFFC0 0C9C DMA3_Y_MODIFY 0xFFC0 0CDC DMA4_Y_MODIFY 0xFFC0 0D1C DMA5_Y_MODIFY 0xFFC0 0D5C DMA6_Y_MODIFY 0xFFC0 0D9C DMA7_Y_MODIFY 0xFFC0 0DDC DMA8_Y_MODIFY 0xFFC0 0E1C DMA9_Y_MODIFY 0xFFC0 0E5C...
Page 233 Direct Memory Access 32-bit register is copied into the DMAx_NEXT_DESC_PTR DMAx_CURR_DESC_ register. Then, during the descriptor fetch, the DMAx_CURR_DESC_PTR register increments after each element of the descriptor is read in. In small and large descriptor list modes, the DMAx_NEXT_DESC_PTR register, and not the register, must be pro- DMAx_CURR_DESC_PTR grammed directly via MMR access before starting DMA operation.
Page 234: Dmax_Curr_Desc_Ptr Mdma_Yy_Curr_Desc_Ptr Registers
DMA Registers Table 5-20. Next Descriptor Pointer Register Memory-mapped Addresses Register Name Memory-mapped Address DMA4_NEXT_DESC_PTR 0xFFC0 0D00 DMA5_NEXT_DESC_PTR 0xFFC0 0D40 DMA6_NEXT_DESC_PTR 0xFFC0 0D80 DMA7_NEXT_DESC_PTR 0xFFC0 0DC0 DMA8_NEXT_DESC_PTR 0xFFC0 0E00 DMA9_NEXT_DESC_PTR 0xFFC0 0E40 DMA10_NEXT_DESC_PTR 0xFFC0 0E80 DMA11_NEXT_DESC_PTR 0xFFC0 0EC0 MDMA_D0_NEXT_DESC_PTR 0xFFC0 0F00 MDMA_S0_NEXT_DESC_PTR 0xFFC0 0F40 MDMA_D1_NEXT_DESC_PTR...
Page 235 Direct Memory Access For descriptor array mode ( ), this register, and not the FLOW = 4 register, must be programmed by MMR DMAx_NEXT_DESC_PTR access before starting DMA operation. Current Descriptor Pointer Registers (DMAx_CURR_DESC_PTR/ MDMA_yy_CURR_DESC_PTR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 For Memory-...
Page 236: Hmdma Registers
DMA Registers Table 5-21. Current Descriptor Pointer Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address DMA7_CURR_DESC_PTR 0xFFC0 0DE0 DMA8_CURR_DESC_PTR 0xFFC0 0E20 DMA9_CURR_DESC_PTR 0xFFC0 0E60 DMA10_CURR_DESC_PTR 0xFFC0 0EA0 DMA11_CURR_DESC_PTR 0xFFC0 0EE0 MDMA_D0_CURR_DESC_PTR 0xFFC0 0F20 MDMA_S0_CURR_DESC_PTR 0xFFC0 0F60 MDMA_D1_CURR_DESC_PTR 0xFFC0 0FA0 MDMA_S1_CURR_DESC_PTR 0xFFC0 0FE0 HMDMA Registers The processor features two HMDMA blocks.
Page 237: Hmdmax_Control Registers
Direct Memory Access Table 5-22. Naming Conventions for Handshake MDMA Registers Handshake MDMA MMR Name (x = 0 or 1) HMDMAx_ECURGENT HMDMAx_ECOVERFLOW HMDMAx_CONTROL Registers The handshake MDMA control register ( , shown in HMDMAx_CONTROL) Figure 5-19, is used to set up HMDMA parameters and operating modes. field is used to control the priority of the MDMA channel DRQ[1:0] when the HMDMA is disabled, that is, when handshake control is not...
Page 238 DMA Registers bit forces the register to be reloaded with the value BCOUNT BCINIT while the module is already active. Do not set this bit in the same write that sets the bit to active. HMDMAEN Handshake MDMA Control Registers (HMDMAx_CONTROL) 15 14 13 12 11 10 HMDMA0: Reset = 0x0200...
Page 239: Hmdmax_Bcinit Registers
Direct Memory Access HMDMAx_BCINIT Registers The handshake MDMA initial block count register ( HMDMAx_BCINIT) shown in Figure 5-20, holds the number of transfers to do per edge of the control signal. DMARx Handshake MDMA Initial Block Count Registers (HMDMAx_BCINIT) 15 14 13 12 11 10 Reset = 0x0000 HMDMA0: 0xFFC0 3308...
Page 240: Hmdmax_Ecount Registers
DMA Registers A block done interrupt is generated when decrements to 0. If the BCOUNT bit in the register is set, the interrupt is suppressed MBDI HMDMAx_CONTROL until is 0. Note if is 0, no block done interrupt is gener- ECOUNT BCINIT ated, since no DMA requests were generated or grants received.
Page 241: Hmdmax_Ecinit Registers
Direct Memory Access Each time that expires, is decremented and BCOUNT ECOUNT BCOUNT reloaded from . When a handshake request edge is detected, BCINIT ECOUNT is incremented. The field is cleared when is disabled. ECOUNT HMDMA Handshake MDMA Current Edge Count Register (HMDMAx_ECOUNT) 15 14 13 12 11 10 Reset = 0x0000 HMDMA0:...
Page 242: Hmdmax_Ecurgent Registers
DMA Registers HMDMAx_ECURGENT Registers The handshake MDMA edge count urgent register ( HMDMAx_ECURGENT) shown in Figure 5-24, holds the urgent threshold. If the field in ECOUNT the handshake MDMA edge count register is greater than this threshold, the MDMA request is urgent and might get higher priority. Handshake MDMA Edge Count Urgent Registers (HMDMAx_ECURGENT) 15 14 13 12 11 10 HMDMA0:...
Page 243: Dma Traffic Control Registers
Direct Memory Access DMA Traffic Control Registers register (see Figure 5-26) and the register (see DMA_TC_PER DMA_TC_CNT Figure 5-27) work with other DMA registers to define traffic control. DMA_TC_PER Register DMA Traffic Control Counter Period Register (DMA_TC_PER) 15 14 13 12 11 10 Reset = 0x0000 MDMA_ROUND_ROBIN_ DCB_TRAFFIC_PERIOD[3:0]...
Page 244: Dma_Tc_Cnt Register
DMA Registers DMA_TC_CNT Register DMA Traffic Control Counter Register (DMA_TC_CNT) 15 14 13 12 11 10 Reset = 0x0000 MDMA_ROUND_ROBIN_ DCB_TRAFFIC_COUNT[3:0] COUNT[4:0] Current cycle count remaining Current transfer count remaining in in the DCB traffic period the MDMA round robin period DEB_TRAFFIC_COUNT[3:0] DAB_TRAFFIC_COUNT[2:0] Current cycle count remaining...
Page 245: Register-Based 2D Memory Dma
Direct Memory Access field shows the current cycle count remaining in DEB_TRAFFIC_COUNT the DEB traffic period. It initializes to whenever DEB_TRAFFIC_PERIOD is written, or whenever the DEB bus changes direction or DMA_TC_PER becomes idle. It then counts down from to 0 on each DEB_TRAFFIC_PERIOD system clock (except for DMA stalls).
Page 246 Programming Examples 10 11 12 20 21 22 23 24 26 27 28 29 Figure 5-28. DMA Example, 2D Array The two arrays reside in two different L1 data memory blocks. However, the arrays could reside in any internal or external memory, including L1 instruction memory and SDRAM.
Page 247 Direct Memory Access _main: p0.l = lo(MDMA_S0_CONFIG); p0.h = hi(MDMA_S0_CONFIG); call memdma_setup; call memdma_wait; _main.forever: jump _main.forever; _main.end: The setup routine shown in Listing 5-2 initializes either MDMA0 or MDMA1 depending on whether the MMR address of MDMA_S0_CONFIG is passed in the register.
Page 248 Programming Examples w[p0 + MDMA_D0_X_MODIFY - MDMA_S0_CONFIG] = r7; r7.l = Y; w[p0 + MDMA_D0_Y_COUNT - MDMA_S0_CONFIG] = r7; r7.l = X; w[p0 + MDMA_D0_X_COUNT - MDMA_S0_CONFIG] = r7; r7.l = -2 * (Y * (X-1) - 1); w[p0 + MDMA_D0_Y_MODIFY - MDMA_S0_CONFIG] = r7; r7.l = DMA2D | DI_EN | WDSIZE_16 | WNR | DMAEN;...
Page 249: Initializing Descriptors In Memory
Direct Memory Access Initializing Descriptors in Memory Descriptor-based DMAs expect the descriptor data to be available in memory by the time the DMA is enabled. Often, the descriptors are pro- grammed by software at run-time. Many times, however, the descriptors—or at least large portions of them—can be static and there- fore initialized at boot time.
Page 250 Programming Examples .byte2 descBlock2.cfg = FLOW_SMALL|NDSIZE_5|DI_EN|WDSIZE_ 16|DMAEN; .byte2 descBlock2.len = length(arrBlock2); descBlock2.end: Another method featured by the VisualDSP++ tools takes advantage of C-style structures in global header files. The header file descriptor.h could look like Listing 5-5. Listing 5-5. Header File to Define Descriptor Structures #ifndef __INCLUDE_DESCRIPTORS__ #define __INCLUDE_DESCRIPTORS__ #ifdef _LANGUAGE_C...
Page 251 Direct Memory Access Note that near pointers are not natively supported by the C language and, thus, pointers are always 32 bits wide. Therefore, the scheme above cannot be used directly for small list mode without giving up pointer syntax. The variable definition file is required to import the C-style header file and can finally take advantage of the structures.
Page 252: Software-Triggered Descriptor Fetch Example
Programming Examples Software-Triggered Descriptor Fetch Example Listing 5-7 demonstrates a large list of descriptors that provide flow stop mode configuration. Consequently, the DMA stops by itself as soon as the work unit has finished. Software triggers the next work unit by simply writing the proper value into the DMA configuration registers.
Page 253 Direct Memory Access .struct dma_desc_list descSource3 = { descSource1, arrSource3, WDSIZE_16 | DMAEN, length(arrSource3), 2, 0, 0 /* unused values */ .struct dma_desc_list descDest1 = { descDest2, arrDest1, DI_EN | WDSIZE_16 | WNR | DMAEN, length(arrDest1), 2, 0, 0 /* unused values */ .struct dma_desc_list descDest2 = { descDest1, arrDest2, DI_EN | WDSIZE_16 | WNR | DMAEN,...
Page 254: Handshaked Memory Dma Example
Programming Examples w[p0 + MDMA_S0_CONFIG - MDMA_S0_CONFIG] = r6; r7.l = FLOW_LARGE|NDSIZE_7|WDSIZE_16|WNR|DMAEN; w[p0 + MDMA_D0_CONFIG - MDMA_S0_CONFIG] = r7; /* wait until destination channel has finished and W1C latch */ _main.wait: r0 = w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] (z); CC = bittst (r0, bitpos(DMA_DONE)); if !CC jump _main.wait;...
Page 255 Direct Memory Access Listing 5-8. HMDMA1 Block Enable /* optionally, enable all four bank select strobes */ p1.l = lo(EBIU_AMGCTL); p1.h = hi(EBIU_AMGCTL); r0.l = 0x0009; w[p1] = r0; /* function enable for DMAR1 */ p1.l = lo(PORTF_FER); r0.l = PF1; w[p1] = r0;...
Page 256 Programming Examples memory DMA. It does not gate requests to the source channel at all. Thus, as soon as the source channel is enabled it starts filling the DMA FIFO immediately. In 16-bit DMA mode this results in eight read strobes on the EBIU even before the first DMAR1 event has been detected.
Page 257: External Bus Interface Unit
6 EXTERNAL BUS INTERFACE UNIT The External Bus Interface Unit (EBIU) provides glueless interfaces to external memories. The processor supports Synchronous DRAM (SDRAM) including mobile SDRAM, and is compliant with the PC100 and PC133 SDRAM standards. The EBIU also supports asynchronous interfaces such as SRAM, ROM, FIFOs, flash memory, and ASIC/FPGA designs.
Page 258 EBIU Overview The EBIU is clocked by the system clock ( ). All synchronous memo- SCLK ries interfaced to the processor operate at the frequency. The ratio SCLK between core frequency and frequency is programmable using a SCLK Phase Locked Loop (PLL) system Memory-Mapped Register (MMR). more information, see “Core Clock/System Clock Ratio Control”...
Page 259 External Bus Interface Unit EXTERNAL MEMORY MAP 0xEEFF FFFF RESERVED 0x2040 0000 ASYNC MEMORY BANK 3 (1 MByte) 0x2030 0000 ASYNC MEMORY BANK 2 (1 MByte) 0x2020 0000 ASYNC MEMORY BANK 1 (1 MByte) 0x2010 0000 ASYNC MEMORY BANK 0 (1 MByte) 0x2000 0000 RESERVED SDRAM MEMORY...
Page 260: Block Diagram
EBIU Overview Block Diagram Figure 6-2 is a conceptual block diagram of the EBIU and its interfaces. Signal names shown with an overbar are active low signals. Since only one external memory device can be accessed at a time, control, address, and data pins for each memory type are multiplexed together at the pins of the device.
Page 261: Internal Memory Interfaces
External Bus Interface Unit Internal Memory Interfaces The EBIU functions as a slave on three buses internal to the processor: • External Access Bus (EAB), mastered by the core memory manage- ment unit on behalf of external bus requests from the core •...
Page 262: Shared Pins
EBIU Overview Registers There are six control registers and one status register in the EBIU. They are: • Asynchronous memory global control register ( EBIU_AMGCTL • Asynchronous memory bank control 0 register ( EBIU_AMBCTL0 • Asynchronous memory bank control 1 register ( EBIU_AMBCTL1 •...
Page 263: System Clock
External Bus Interface Unit System Clock pin is shared by both the SDC and AMC. Two different regis- CLKOUT ters are used to control this: • register, bit for SDC clock EBIU_SDGCTL SCTLE • register, bit for AMC clock EBIU_AMGCTL AMCKEN If enabling or disabling the system clock, software control for both regis- ters is required.
Page 264: Bus Request And Grant
EBIU Overview Bus Request and Grant The processor can relinquish control of the data and address buses to an external device. The processor three-states its memory interface to allow an external controller to access either external asynchronous or synchro- nous memory parts. Operation When the external device requires access to the bus, it asserts the bus request (...
Page 265: Amc Overview And Features
External Bus Interface Unit AMC Overview and Features The following sections describe the features of the AMC. Features The EBIU AMC features include: • I/O width 16-bit, I/O supply 2.5 or 3.3 V • Maximum throughput of 133 M bytes/second •...
Page 266: Asynchronous Memory Address Decode
AMC Pin Description Table 6-1. Asynchronous Memory Bank Address Range Memory Bank Select Address Start Address End AMS[3] 0x2030 0000 0x203F FFFF AMS[2] 0x2020 0000 0x202F FFFF AMS[1] 0x2010 0000 0x201F FFFF AMS[0] 0x2000 0000 0x200F FFFF Asynchronous Memory Address Decode The address range allocated to each asynchronous memory bank is fixed at 1M byte;...
Page 267: Amc Description Of Operation
External Bus Interface Unit Table 6-2. Asynchronous Memory Interface Signals (Cont’d) Pin Type Description Asynchronous memory write enable Asynchronous memory read enable Asynchronous memory output enable In most cases, the AOE pin should be connected to the OE pin of an external memory-mapped asynchronous device.
Page 268: External Access Extension
AMC Functional Description memory spaces. In this case, the two memory devices addressed by the two reads could potentially contend at the transition between the two read operations. To avoid contention, program the turnaround time (bank transition time) appropriately in the asynchronous memory bank control registers. This feature allows software to set the number of clock cycles between these types of accesses on a bank-by-bank basis.
Page 269: Asynchronous Reads
External Bus Interface Unit Asynchronous Reads Figure 6-3 shows an asynchronous read bus cycle with timing pro- grammed as setup = 2 cycles, read access = 2 cycles, hold = 1 cycle, and transition time = 1 cycle. Asynchronous read bus cycles proceed as follows. 1.
Page 270: Asynchronous Writes
AMC Functional Description TRANSITION SETUP READ ACCESS HOLD TIME 2 CYCLES 2 CYCLES 1 CYCLE 1 CYCLE CLKOUT [3:0] [1:0] ADDR[19:1] DATA[15:0] Figure 6-3. Asynchronous Read Bus Cycles Asynchronous Writes Figure 6-4 shows an asynchronous write bus cycle followed by an asyn- chronous read cycle to the same bank, with timing programmed as setup = 2 cycles, write access = 2 cycles, read access = 3 cycles, hold = 1 cycle, and transition time = 1 cycle.
Page 271 External Bus Interface Unit DATA LATCHED TRANSITION SETUP WRITE ACCESS HOLD SETUP READ ACCESS HOLD TIME 2 CYCLES 2 CYCLES 1 CYCLE 2 CYCLES 3 CYCLES 1 CYCLE 1 CYCLE CLKOUT [1:0] ADDR[19:1] DATA[15:0] Figure 6-4. Asynchronous Write and Read Bus Cycles Asynchronous write bus cycles proceed as follows.
Page 272: Adding External Access Extension
AMC Functional Description Asynchronous read bus cycles proceed as follows. 1. At the start of the setup period, assert. The address AMS[x] bus becomes valid. The signals are low during the read. ABE[1:0] 2. At the beginning of the read access period, asserts.
Page 273 External Bus Interface Unit SETUP PROGRAMMED READ ACCESS ACCESS EXTENDED HOLD 2 CYCLES 4 CYCLES 3 CYCLES 1 CYCLE DATA READY SAMPLED LATCHED CLKOUT [1:0] ADDRESS ADDR[19:1] DATA[15:0] READ D ARDY Figure 6-5. Inserting Wait States Using ARDY ADSP-BF537 Blackfin Processor Hardware Reference 6-17...
Page 274: Byte Enables
AMC Programming Model Byte Enables The AMC provides byte enable pins to allow the processor to perform efficient byte-wide arithmetic and byte-wide processing in external memory. In general, there are two different ways to modify a single byte within the 16-bit interface.
Page 275 External Bus Interface Unit programmed while the AMC is in use. The register should be EBIU_AMGCTL the last control register written to when configuring the processor to access external memory-mapped asynchronous devices. Additional information for the register bits includes: EBIU_AMGCTL •...
Page 276 AMC Programming Model The EBIU asynchronous memory controller has two asynchronous mem- ory bank control registers ( ). They EBIU_AMBCTL0 EBIU_AMBCTL1 contain bits for counters for setup, strobe, and hold time; bits to deter- mine memory type and size; and bits to configure use of .
Page 277: Amc Registers
External Bus Interface Unit AMC Registers The following sections describe the AMC registers. EBIU_AMGCTL Register Figure 6-6 shows the asynchronous memory global control register EBIU_AMGCTL Asynchronous Memory Global Control Register (EBIU_AMGCTL) 15 14 13 12 11 10 0xFFC0 0A00 Reset = 0x00F2 CDPRIO AMCKEN 0 - Disable CLKOUT for...
Page 278 AMC Registers Asynchronous Memory Bank Control 0 Register (EBIU_AMBCTL0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0A04 Reset = 0xFFC2 FFC2 B1RDYEN B1WAT[3:0] Bank 1 write access time (number of Bank 1 ARDY enable cycles AWE is held asserted) 0 - Ignore ARDY for accesses to...
Page 279 External Bus Interface Unit Asynchronous Memory Bank Control 1 Register (EBIU_AMBCTL1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0xFFC2 FFC2 0xFFC0 0A08 B3WAT[3:0] B3RDYEN Bank 3 write access time (number of Bank 3 ARDY enable cycles AWE is held asserted) 0 - Ignore ARDY for accesses to...
Page 280: Amc Programming Examples
AMC Programming Examples AMC Programming Examples Listing 6-1 Listing 6-2 provide examples for working with the AMC. Listing 6-1. 16-Bit Core Transfers to SRAM .section L1_data_b; .byte2 source[N] = 0x1122, 0x3344, 0x5566, 0x7788; .section SRAM_bank_0; .byte2 dest[N]; .section L1_code; I0.L = lo(source); I0.H = hi(source);...
Page 281: Sdc Overview And Features
External Bus Interface Unit start: R0 = b[p0++](z); end: b[p1++] = R0; /* byte data masking */ SDC Overview and Features The SDRAM Controller (SDC) enables the processor to transfer data to and from Synchronous DRAM (SDRAM) with a maximum frequency specified in the product data sheet.
Page 282: Sdram Configurations Supported
SDC Overview and Features • Uses a programmable refresh counter to coordinate between vary- ing clock frequencies and the SDRAM’s required refresh rate • Provides multiple timing options to support additional buffers between the processor and SDRAM • Allows independent auto-refresh while the asynchronous memory controller has control of the EBIU port •...
Page 283: Sdram External Bank Size
External Bus Interface Unit Table 6-4. SDRAM Discrete Component Configurations Supported (Cont’d) System Size System Size SDRAM Number of (M byte) (M bit) Configuration Chips 64M x 16 64M x 4 64M x 16 64M x 8 64M x 16 64M x 16 128M x 16 128M x 4...
Page 284 SDC Overview and Features on page 6-40.) It starts with address 0x0 for internal bank A and ends with the last valid address (specified with parameters) contain- EBSZ EBCAW ing the internal bank D. The internal 29-bit non-multiplexed address (See Figure 6-9) is multi- plexed into:...
Page 285: Internal Sdram Bank Select
External Bus Interface Unit Internal SDRAM Bank Select The internal SDRAM banks are driven by the ADSP-BF537’s which are part of the row and column address and connected ADDR[19:18] to the SDRAM’s BA[1:0] Do not flip up both internal bank select connections, if using the mobile SDRAM’s PASR feature.
Page 286: Sdc Interface Overview
SDC Interface Overview SDC Interface Overview The following sections describe the SDC interface. SDC Pin Description The SDRAM interface signals are shown in Table 6-6. Table 6-6. SDRAM Interface Signals Pin Type Description DATA[15:0] External data bus ADDR[19:18], External address bus ADDR[16:12], Connect to SDRAM address pins.
Page 287: Sdram Performance
External Bus Interface Unit Table 6-6. SDRAM Interface Signals (Cont’d) Pin Type Description SCKE SDRAM clock enable pin Connect to SDRAM’s CKE pin. CLKOUT SDRAM clock output pin Switches at system clock frequency. Connect to the SDRAM’s CLK pin. 1 Pin Types: I = Input, O = Output SDRAM Performance On-page sequential or non-sequential accesses are from internal data memory to SDRAM.
Page 288: Sdc Description Of Operation
SDC Description of Operation Off-page accesses are summarized in Table 6-9. Table 6-9. SDRAM Stall Cycles For Off-Page Accesses Type of access Stall Cycles Write Read + CL SDC Description of Operation The following sections describe the operation of the SDC. Definition of SDRAM Architecture Terms The following are definitions of SDRAM architecture terms used in the remainder of this chapter.
Page 289: Row Precharge
External Bus Interface Unit Row Precharge If the next access is in a different row, the current row is closed before another is opened. The current “row cache” is written back to the row. This is called row precharge. Internal Bank There are up to 4 internal memory banks on a given SDRAM.
Page 290: Burst Type
SDC Description of Operation Burst Type The burst type determines the address order in which the SDRAM deliv- ers burst data. The burst type is selected by writing the bits in the SDRAM’s mode register during the SDRAM powerup sequence. CAS Latency The CAS latency or read latency specifies the time between latching a read address and driving the data off chip.
Page 291: Bank Activate Command
External Bus Interface Unit Bank Activate command The bank activate command causes the SDRAM to open an internal bank (specified by the bank address) in a row (specified by the row address). When the bank activate command is issued, it opens a new row address in the dedicated bank.
Page 292: Exit Self-Refresh Mode
SDC Description of Operation Exit Self-Refresh Mode When the SDRAM exits self-refresh mode, the SDRAM’s internal timer stops refresh cycles and relinquishes control to external SDC. SDC Timing Specs The following SDRAM timing specs are discussed because they are used by the SDC and SDRAM.
Page 293: Trcd
External Bus Interface Unit The CAS latency or read latency is the delay between when the SDRAM detects the read command and when it provides the data off-chip. This spec does not apply to writes. Dependency: system clock frequency and speed grade SDC setting: 2–3 normalized system clock cycles SDC usage: first read command...
Page 294: Trfc
SDC Description of Operation This is the required delay between a bank A precharge command and a bank A activation command. Dependency: system clock frequency SDC setting: 1–7 normalized system clock cycles SDC usage: off-page read/write, auto-refresh, self-refresh command This is the required delay between issuing successive bank activate commands.
Page 295: Tref
External Bus Interface Unit This is the row refresh period, and typically takes 64 ms. Dependency: system clock frequency SDC setting: none SDC usage: auto-refresh command REFI This is the row refresh interval and typically takes 15.6 ms for < 8k rows and 7.8 ms for >= 8k rows.
Page 296 SDC Functional Description The configuration is programmed in the register. The SDRAM SDBCTL controller can hold off the processor core or DMA controller with an internally connected acknowledge signal, as controlled by refresh, or page miss latency overhead. A programmable refresh counter is provided which generates background auto-refresh cycles at the required refresh rate based on the clock fre- quency used.
Page 297 External Bus Interface Unit The internal 32-bit non-multiplexed address is multiplexed into: • Data mask for bytes • SDRAM column address • SDRAM row address • Internal SDRAM bank address is used for 8-bit wide SDRAMs to generate the data masks. The A[0] next lowest bits are mapped into the column address, next bits are mapped into the row address, and the final two bits are mapped into the internal...
Page 298: Sdc Address Muxing
SDC Functional Description SDC Address Muxing Table 6-10 shows the connection of the address pins with the SDRAM device pins. Table 6-10. SDRAM Address Connections for 16-bit Banks External Address Pin SDRAM Address Pin ADDR[19] BA[1] ADDR[18] BA[0] ADDR[16] A[15] ADDR[15] A[14] ADDR[14]...
Page 299: Multibank Operation
External Bus Interface Unit Multibank Operation Since an SDRAM contains 4 independent internal banks (A-D), the SDC is capable of supporting multibank operation thus taking advantage of the architecture. Any first access to SDRAM bank (A) will force an activate command before a read or write command.
Page 300: Core And Dma Arbitration
SDC Functional Description SINGLE BANK MULTIBANK OPERATION OPERATION ACCESS TO PAGE X ACCESS TO PAGE X BANK A BANK A ACCESS TO PAGE Y ACCESS TO PAGE Y BANK B BANK B ACCESS TO PAGE X BANK C BANK C ACCESS TO PAGE Y BANK D BANK D...
Page 301 External Bus Interface Unit The reduction of system clock will violate the minimum specs, while increasing system clock will violate the maximum t spec. Therefore, careful software control is required to adapt these changes. For most applications, the SDRAM powerup sequence and writing of the mode register needs to be done only once.
Page 302: Changing Power Management During Runtime
SDC Functional Description 4. Reprogram the SDRAM registers with values appropriate to the frequency, and assure that the bit is set. SCLK PSSE 5. Bring the SDRAM out of self-refresh mode by clearing the SRFS EBIU_SDGCTL Changing Power Management During Runtime Deep Sleep Mode During deep sleep mode, the core and system clock will halt.
Page 303: Sdc Commands
External Bus Interface Unit 3. Host enters self-refresh mode. 4. Programmable flag driven from host will trigger an ISR which sets the bit to cause the ADSP-BF537 to enter self-refresh SFRS mode. 5. Host deasserts pin which is granted with pin.
Page 304 SDC Functional Description • Auto-refresh • Self-refresh • NOP Table 6-11 shows the SDRAM pin state during SDC commands. Table 6-11. Pin State During SDC Commands Command SCKE SCKE SRAS SCAS SA10 Addresses (n - 1) (E)/Mode High High Op-code Op-code register set Activate...
Page 305: Mode Register Set Command
External Bus Interface Unit Table 6-11. Pin State During SDC Commands (Cont’d) Command SCKE SCKE SRAS SCAS SA10 Addresses (n - 1) High High High High High Don’t Don’t care care Inhibit High High High Don’t Don’t Don’t Don’t Don’t care care Care care...
Page 306 SDC Functional Description sequence to be run, which programs the SDRAM’s mode register with burst length, burst type, and CAS latency from the register EBIU_SDGCTL and optionally the content to the extended mode register. This initial read or write to SDRAM takes many cycles to complete. While executing an MRS command, the unused address pins are set to 0.
Page 307: Bank Activation Command
External Bus Interface Unit Bank Activation Command The bank activation command is required for first access to any internal bank in SDRAM. Any subsequent access to the same internal bank but different row will be preceded by a precharge and activation command to that bank.
Page 308: Single Precharge Command
SDC Functional Description During read transfers to SDRAM banks, reads are always done of all bytes in the bank regardless of the transfer size. This means for 16-bit SDRAM banks, are all 0s. SDQM[1:0] Table 6-12. SDQM[1:0] Encodings During Writes Internal Address Internal Transfer Size IA[0]...
Page 309: Self-Refresh Mode
External Bus Interface Unit SDC refresh counter times out. The value in the SDRAM refresh RDIV rate control register must be set so that all addresses are refreshed within the t period specified in the SDRAM timing specifications. This com- mand is issued to the external bank whether or not it is enabled ( in the SDRAM memory global control register).
Page 310: Self-Refresh Exit Command
SDC Functional Description Self-Refresh Exit Command Leaving self-refresh mode is performed with the self-refresh exit com- mand, whereby the SDC asserts . Any internal core/DMA access SCKE causes the SDC to perform an exit self-refresh command. The SDC waits to meet the t specification (t ) and then issues an auto-refresh command.
Page 311: Sdc Sa10 Pin
External Bus Interface Unit When the SDC is actively accessing the SDRAM to insert additional wait states, the NOP command is given. When the SDC is not accessing the SDRAM, the command inhibit command is given ( SDC SA10 Pin The SDRAM’s pin follows the truth table below: A[10]...
Page 312: Sdc Configuration
SDC Programming Model SDC Configuration After a processor’s hardware or software reset, the SDC clocks are enabled; however, the SDC must be configured and initialized. Before program- ming the SDC and executing the powerup sequence, these steps are required: 1. Ensure the clock to the SDRAM is stable after the power has stabi- lized for the proper amount of time (typically 100 μs).
Page 313 External Bus Interface Unit After the SDRAM powerup sequence has completed, if the external bank is disabled, any transfer to it results in a hardware error interrupt, and the SDRAM transfer does not occur. register is written: EBIU_SDGCTL • To set the SDRAM cycle timing options ( TRAS TRCD EBUFE...
Page 314: Example Sdram System Block Diagrams
SDC Programming Model Example SDRAM System Block Diagrams Figure 6-12 shows a block diagram of an SDRAM interface. In this exam- ple, the SDC connected to 2 x (8M x 8) = 8M x 16 to form one external bank of 128Mbit / 16Mbyte of memory. The system’s page size is 1024 bytes.
Page 315 External Bus Interface Unit Figure 6-13 shows a block diagram of an SDRAM interface. In this exam- ple, the SDC connected to 4 x (16M x 4) = 16M x 16 to form one external bank of 256Mbit / 32Mbyte of memory. The system’s page size is 2048 bytes.
Page 316: Sdc Register Definitions
SDC Register Definitions SDC Register Definitions The following sections describe the SDC registers. EBIU_SDRRC Register The SDRAM refresh rate control register ( , shown in EBIU_SDRRC Figure 6-14) provides a flexible mechanism for specifying the auto-refresh timing. Since the clock supplied to the SDRAM can vary, the SDC pro- vides a programmable refresh counter, which has a period based on the value programmed into the field of this register.
Page 317 External Bus Interface Unit Where: • f = SDRAM clock frequency (system clock frequency) SCLK • t = SDRAM row refresh period • t = SDRAM row refresh interval REFI • NRA = Number of row addresses in SDRAM (refresh cycles to refresh whole SDRAM) •...
Page 318: Ebiu_Sdbctl Register
SDC Register Definitions The equation for yields: RDIV = ( (133 x 10 x 64 x 10 ) / 8192) – (6 + 3) = 1030 clock RDIV cycles This means is 0x406 (hex) and the SDRAM refresh rate control reg- RDIV ister should be written with 0x406.
Page 319 External Bus Interface Unit configurations. Table 6-13 maps SDRAM density and I/O width. “SDRAM External Bank Size” on page 6-27 for more informa- tion on bank starting address decodes. • External bank column address width ( EBCAW The SDC determines the internal SDRAM page size from the parameters.
Page 320 SDC Register Definitions The page size can be calculated for 16-bit SDRAM banks with this formula: (CAW + 1) page size = 2 where is the column address width of the SDRAM, plus 1 because the SDRAM bank is 16 bits wide (1 address bit = 2 bytes). Table 6-13.
Page 321: Using Sdrams With Systems Smaller Than 16M Byte
External Bus Interface Unit Table 6-13. Internal Address Mapping (Cont’d) Page IA[24:23] IA[22:9] IA[8:1] IA[0] IA[23:22] IA[21:12] IA[11:1] IA[0] IA[23:22] IA[21:11] IA[10:1] IA[0] IA[23:22] IA[21:10] IA[9:1] IA[0] IA[23:22] IA[21:9] IA[8:1] IA[0] The minimum column width for a 256M byte SDRAM configura- tion is 9 and the minimum column width for a 512M byte SDRAM configuration is 10.
Page 322 SDC Register Definitions Referring to the table in Figure 6-16, note that each line in the table cor- responds to 2 bytes, or 512K byte. Thus, the mapping of the 2M byte SDRAM is noncontiguous in Blackfin memory, as shown by the memory mapping in the left side of the figure.
Page 323: Ebiu_Sdgctl Register
External Bus Interface Unit EBIU_SDGCTL Register The SDRAM memory global control register ( ) includes all EBIU_SDGCTL programmable parameters associated with the SDRAM access timing and configuration. Figure 6-17 shows the register bit definitions. EBIU_SDGCTL • SDRAM clock enable ( SCTLE bit is used to enable or disable the SDC.
Page 324 SDC Register Definitions SDRAM Memory Global Control Register (EBIU_SDGCTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0A10 Reset = 0xE008 8849 TRCD[2:1] SDRAM t in SCLK cycles CDDBG 000 - Reserved Control disable during bus grant 001-111 - 1 to 7 cycles 0 - Continue driving SDRAM...
Page 325 External Bus Interface Unit If an access occurs to the SDRAM address space while is 0, SCTLE the access generates an internal bus error and the access does not occur externally. For more information, see “Error Detection” on page 6-7. With careful software control, the bit can be used in con- SCTLE...
Page 326 SDC Register Definitions • Partial array self refresh ( PASR bits determine how many internal SDRAM banks are PASR refreshed during self-refresh. • PASR = 00 All 4 banks • PASR = 01 Internal banks 0 and 1 refreshed • PASR = 10 Only internal bank 0 refreshed •...
Page 327 External Bus Interface Unit • Bank precharge delay ( bits in the SDRAM memory global control register ) select the t value. Any value between 1 and 7 EBIU_SDGCTL clock cycles may be selected. For example: • TRP = 000 No effect •...
Page 328 SDC Register Definitions • Write to precharge delay ( bits in the SDRAM memory global control register ) select the t value. Any value between 1 and 3 EBIU_SDGCTL clock cycles may be selected. For example: • TWR = 00 Reserved •...
Page 329 External Bus Interface Unit If the bit is set to 0, the SDC command sequence is: 1. Precharge all 2. 8 auto-refresh cycles 3. Mode register set • Powerup sequence start enable ( PSSE bits work together to specify and trigger an PSSE SDRAM powerup (initialization) sequence.
Page 330 SDC Register Definitions • Self-refresh setting ( SRFS bits work together in SRFS SCTLE EBIU_SDGCTL self-refresh control: • SRFS = 0 Disable self-refresh mode • SRFS = 1 Enter self-refresh mode When is set to 1, self-refresh mode is triggered. Once the SRFS SDC completes any active transfers, the SDC executes a sequence of commands to put the SDRAM into self-refresh mode.
Page 331 External Bus Interface Unit Exit Self-Refresh Mode The SDRAM device exits self-refresh mode only when the SDC receives core or DMA requests. In conjunction with the bit, 2 SRFS possibilities are given to exit self-refresh mode: 1. If the bit keeps set before the core/DMA request, the SDC SRFS exits self-refresh mode temporarily for a single request and returns back to self-refresh mode until a new request is latched.
Page 332 SDC Register Definitions bit in the register enables this mode: EBUFE EBIU_SDGCTL • EBUFE = 0 Disable external buffering timing • EBUFE = 1 Enable external buffering timing When , the SDRAM controller delays the data in write EBUFE = 1 accesses by one cycle, enabling external buffer registers to latch the address and controls.
Page 333 External Bus Interface Unit • Temperature compensated self-refresh ( TCSR bit signals to the SDRAM the worst case temperature TCSR range for the system, and thus how often the SDRAM internal banks need to be refreshed during self-refresh. • Control disable during bus grant ( CDDBG bit is used to enable or disable the SDRAM control sig- CDDBG...
Page 334: Ebiu_Sdstat Register
SDC Register Definitions EBIU_SDSTAT Register The SDRAM control status register ( ), shown in Figure 6-18, EBIU_SDSTAT provides information on the state of the SDC. This information can be used to determine when it is safe to alter SDC control parameters or it can be used as a debug aid.
Page 335: Sdc Programming Examples
External Bus Interface Unit • SDC powerup active ( SDPUA If the bit is 0, the SDC is not in powerup sequence. If the SDPUA bit is 1, the SDC performs the powerup sequence. SDPUA • SDC powerup delay ( SDRS If the bit is 0, the SDC has already powered up.
Page 336 SDC Programming Examples I0.H = hi(source); I1.L = lo(dest); I1.H = hi(dest); R0.L = w[I0++]; p5=N-1; lsetup(lp, lp) lc0=p5; lp:R0.L = w[I0++] || w[I1++] = R0.L; w[I1++] = R0.L; Listing 6-4. 8-Bit Core Transfers to SDRAM Using Byte Mask SDQM[1:0] Pins .section L1_data_b;...
Page 337 External Bus Interface Unit Listing 6-5. Self-Refresh Mode Power Savings With Disabled CLKOUT r0.l = w[I1++]; /* SDRAM access */ ssync; /* force last SDRAM access to finish */ P0.L = lo(EBIU_SDGCTL); P0.H = hi(EBIU_SDGCTL); R1 = [P0]; bitset(R1, bitpos(SRFS)); /* enter self-refresh */ [P0] = R1;...
Page 338 SDC Programming Examples [P0] = R1; ssync; R1 = [P0]; bitclr(R1, bitpos(SRFS)); /* exit self-refresh */ [P0] = R1; ssync; w[I1++] = r0.l; /* SDRAM access */ Listing 6-6. Init /*********************************************************/ /* SDRAM part# Micron MT48LC32M8A2-75 (32Mx8/256Mbit) */ /* 8k rows, 1k columns ->...
Page 339 External Bus Interface Unit /* Check if already enabled */ p0.l = lo(EBIU_SDSTAT); p0.h = hi(EBIU_SDSTAT); r0 = [p0]; cc = bittst(r0, bitpos(SDRS)); if !cc jump skip init_sdram; /* SDRAM Refresh Rate Control Register */ P0.L = lo(EBIU_SDRRC); P0.H = hi(EBIU_SDRRC); R0.L = 0x0406;...
Page 340 SDC Programming Examples 6-84 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 341: Overview
7 PARALLEL PERIPHERAL INTERFACE This chapter describes the Parallel Peripheral Interface (PPI). Following an overview and a list of key features are a description of operation and functional modes of operation. The chapter concludes with a program- ming model, consolidated register definitions, and programming examples.
Page 342: Interface Overview
Interface Overview Typical peripheral devices that can be interfaced to the PPI port: • A/D converters • D/A converters • LCD panels • CMOS sensors • Video encoders • Video decoders Interface Overview Figure 7-1 shows a block diagram of the PPI. PPI_CONTROL PPI_CLK PPI_COUNT...
Page 343 Parallel Peripheral Interface pin accepts an external clock input. It cannot source a clock PPI_CLK internally. When the is not free-running, there may be additional PPI_CLK latency cycles before data gets received or transmitted. In RX and TX modes, there may be at least 2 cycles latency before valid data is received or transmitted.
Page 344 Interface Overview All pins of port F and port G function as GPIOs by default and must be individually enabled for either PPI or any other peripheral operation by setting the appropriate bits in the function enable registers PORTF_FER . For more information, refer to Chapter 14, “General-Purpose PORTG_FER Ports”.
Page 345: Description Of Operation
Parallel Peripheral Interface Table 7-1. PPI Pins (Cont’d) Pin Name (Function) PORT_MUX PORTF_FER PORTG_FER PPI_FS2 (PPI frame sync 2) Set bit 8 (PF8) PPI_FS3 (PPI frame sync 3) Set bit 8 (PFFE) Set bit 7 (PF7) Description of Operation Table 7-2 shows all the possible modes of operation for the PPI.
Page 346: Functional Description
Functional Description Table 7-2. PPI Possible Operating Modes (Cont’d) PPI Mode # of PORT PORT XFR_ POLC POLS FLD_ Syncs _DIR _CFG TYPE TX mode, 2 external frame 0 or 1 0 or 1 syncs TX mode, 2 or 3 internal 0 or 1 0 or 1 frame syncs, FS3 sync’d to...
Page 347 Parallel Peripheral Interface Video (EAV) signals indicate the beginning and end of data elements to read in on each line. SAV occurs on a 1-to-0 transition of H, and EAV begins on a 0-to-1 transition of H. An entire field of video is comprised of active video + horizontal blanking (the space between an EAV and SAV code) and vertical blanking (the space where V = 1).
Page 348 Functional Description LINE # LINE 4 VERTICAL BLANKING LINE FI ELD 1 (EAV) (SAV) NUMBER FIELD 1 1-3, ACTIVE VIDEO 266-282 LINE 266 4-19, VERTICAL 264-265 BLANKING FI ELD 2 20-263 FIELD 2 283-525 ACTIVE VIDEO LINE 3 LINE 1 VERTICAL BLANKING FI ELD 1...
Page 349 Parallel Peripheral Interface • during vertical blanking V = 1 • when not in vertical blanking V = 0 • at SAV H = 0 • at EAV H = 1 • P3 = V XOR H • P2 = F XOR H •...
Page 350: Itu-R 656 Input Modes
Functional Description ITU-R 656 Input Modes Figure 7-4 shows a general illustration of data movement in the ITU-R 656 input modes. In the figure, the clock is either provided by the video source or supplied externally by the system. ITU-R 656 INPUT MODE '656 8- OR 10-BIT DATA WITH PPIx...
Page 351: Active Video Only
Parallel Peripheral Interface Data transfer starts immediately after synchronization to field 1 occurs, but does not include the first EAV code that contains the F = 0 assignment. Note the first line transferred in after enabling the PPI will be miss- ing its first 4-byte preamble.
Page 352: Itu-R 656 Output Mode
Functional Description Control byte sequence information is always logged. The user specifies the number of total lines (active plus vertical blanking) per frame in the MMR. PPI_FRAME Note the VBI is split into two regions within each field. From the PPI’s standpoint, it considers these two separate regions as one contiguous space.
Page 353: General-Purpose Ppi Modes
Parallel Peripheral Interface Because all H and V signalling is embedded in the datastream in ITU-R 656 modes, the register is not necessary. However, the PPI_COUNT register is used in order to check for synchronization errors. PPI_FRAME The user programs this MMR for the number of lines expected in each frame of video, and the PPI keeps track of the number of EAV-to-SAV transitions that occur from the start of a frame until it decodes the end-of-frame condition (transition from F = 1 to F = 0).
Page 354 Functional Description Table 7-4. General-Purpose PPI Modes (Cont’d) GP PPI Mode PPI_FS1 PPI_FS2 PPI_FS3 Data Direction Direction Direction Direction RX mode, 2 or 3 external frame syncs Input Input Input (if Input used) RX mode, 2 or 3 internal frame syncs Output Output Output (if Input...
Page 355: Data Input (Rx) Modes
Parallel Peripheral Interface . Next, the DMA controller transfers out the number of samples PPI_DELAY specified by . No further DMA takes place until the next PPI_COUNT sync and programmed delay occur. PPI_FS1 If the next frame sync arrives before the specified PPI_FS1 samples have been transferred out, the sync has priority PPI_COUNT...
Page 356: No Frame Syncs
Functional Description No Frame Syncs These modes cover the set of applications where periodic frame syncs are not generated to frame the incoming data. There are two options for start- ing the data transfer, both configured by the register. PPI_CONTROL •...
Page 357: Or 3 Internal Frame Syncs
Parallel Peripheral Interface CONVERTER PPI_FS1 FRAMESYNC 8–16 BITS DATA PPIx DATA PPI_CLK VIDEO SOURCE PPI_FS1 HSYNC PPI_FS2 VSYNC PPI_FS3 FIELD DATA 8–16 BITS DATA PPIx PPI_CLK Figure 7-7. RX Mode, External Frame Syncs A 2-sync mode is supported by not enabling the third frame sync pin in registers.
Page 358: Data Output (Tx) Modes
Functional Description Data Output (TX) Modes The PPI supports several modes for data output. These modes differ chiefly by the way the data is framed. Refer to Table 7-2 on page 7-5 information on how to configure the PPI for each mode. No Frame Syncs In this mode, data blocks specified by the DMA controller are sent out through the PPI with no framing.
Page 359: Or 3 Internal Frame Syncs
Parallel Peripheral Interface There is a mandatory delay of 1.5 cycles, plus the value PPI_CLK programmed in , between assertion of the external frame PPI_DELAY sync(s) and the transfer of valid data out through the PPI. DATA RECEIVER FRAMESYNC PPI_FS1 PPIx DATA 8–16 BITS DATA...
Page 360: Frame Synchronization In Gp Modes
Functional Description CONVERTER FRAMESYNC PPI_FS1 1 FRAME 8–16 BITS DATA PPIx DATA SYNC PPI_CLK VIDEO DISPLAY PPI_FS1 HSYNC VSYNC PPI_FS2 FIELD PPI_FS3 3 FRAME SYNCS PPIx 8–16 BITS DATA PPI_CLK Figure 7-11. PPI GP Output Frame Synchronization in GP Modes Frame synchronization in GP modes operates differently in modes with internal frame syncs than in modes with external frame syncs.
Page 361: Modes With External Frame Syncs
Parallel Peripheral Interface To program and/or for operation in an internal PPI_FS1 PPI_FS2 frame sync mode: 1. Configure and enable DMA for the PPI. See “DMA Operation” on page 7-23. 2. Configure the width and period for each frame sync signal via (for ), or TIMER0_WIDTH...
Page 362 Functional Description 1 is not restricted in functionality and can be operated as if the PPI were not being used (that is, the pin becomes available for timer use as TMR1 well). For more information on configuring and using the timers, please refer to Chapter 15, “General-Purpose Timers”.
Page 363: Programming Model
Parallel Peripheral Interface Programming Model The following sections describe the PPI programming model. DMA Operation The PPI must be used with the processor’s DMA engine. This section dis- cusses how the two interact. For additional information about the DMA engine, including explanations of DMA registers and DMA operations, please refer to Chapter 5, “Direct Memory Access”.
Page 364 Programming Model assume the DMA registers . Then, if a data frame XMODIFY = YMODIFY = 1 contains 320 x 240 bytes (240 rows of 320 bytes each), these conditions hold: • Setting , and (the XCOUNT = 320 YCOUNT = 240 DI_SEL = 1 DI_SEL bit is located in...
Page 365 Parallel Peripheral Interface START PROGRAM 2D DMA? Y_COUNT AND Y_MODIFY WRITE 3 FS? PORT_MUX WRITE PORTF_FER AND PORTG_FER PROGRAM PPI_DELAY PROGRAM TIMER(S) EXTERNAL INTERNAL FS? LINKED WITH FS TRIGGER? PROGRAM PPI_FRAME PROGRAM PPI_COUNT WRITE DMAx_CONFIG TO ENABLE DMA WRITE PPI_CONTROL TO ENABLE PPI WRITE TIMER_ENABLE TO ENABLE TIMERS INTERNAL FS? Figure 7-12.
Page 366: Ppi Registers
PPI Registers PPI Registers The PPI has five memory-mapped registers (MMRs) that regulate its oper- ation. These registers are the PPI control register ( ), the PPI PPI_CONTROL status register ( ), the delay count register ( ), the PPI_STATUS PPI_DELAY transfer count register ( ), and the lines per frame register...
Page 367 Parallel Peripheral Interface PPI Control Register (PPI_CONTROL) 15 14 13 12 11 10 0xFFC0 1000 Reset = 0x0000 POLS PORT_EN (Enable) 0 - PPI_FS1 and 0 - PPI disabled PPI_FS2 are treated 1 - PPI enabled as rising edge PORT_DIR (Direction) asserted 0 - PPI in Receive mode (input) 1 - PPI_FS1 and...
Page 368 PPI Registers When the bit is set, the bit allows the PPI to ignore SKIP_EN SKIP_EO either the odd or the even elements in an input datastream. This is useful, for instance, when reading in a color video signal in YCbCr format (Cb, Y, Cr, Y, Cb, Y, Cr, Y...).
Page 369 Parallel Peripheral Interface • With cleared: PACK_EN This is read into the PPI: 0xCE, 0xFA, 0xFE, 0xCA, ... This is transferred onto the DMA bus: 0x00CE, 0x00FA, 0x00FE, 0x00CA, ... For TX modes, setting enables unpacking of bytes. Consider this PACK_EN data in memory, to be transported out through the PPI via DMA: (0xFA and 0xCA are the two Most Significant Bits...
Page 370: Ppi_Status Register
PPI Registers bit is used primarily in the active field only ITU-R 656 FLD_SEL mode. The bit determines whether to transfer in only field 1 of FLD_SEL each video frame, or both fields 1 and 2. Thus, it allows a savings in DMA bandwidth by transferring only every other field of active video.
Page 371 Parallel Peripheral Interface bit is sticky and is relevant only in ITU-R 656 modes. If ERR_NCOR , all preamble errors that have occurred ERR_NCOR = 0 ERR_DET = 1 have been corrected. If , an error in the preamble was ERR_NCOR = 1 detected but not corrected.
Page 372 PPI Registers modes) or “Start of Active Video (SAV)” codes (for ITU-R 656 modes). If the PPI error interrupt is enabled in the register, an interrupt SIC_IMASK request is generated when one of these bits is set. flag signifies that a horizontal tracking overflow has LT_ERR_OVR occurred, where the value in was reached before a new SAV...
Page 373 Parallel Peripheral Interface PPI Status Register (PPI_STATUS) 15 14 13 12 11 10 0xFFC0 1004 Reset = 0x0000 LT_ERR_OVR (Horizontal ERR_NCOR (Error Not Corrected) Tracking Overflow Error) - - W1C Used only in ITU-R 656 Used only in ITU-R 656 modes modes 0 - No uncorrected...
Page 374: Ppi_Delay Register
PPI Registers PPI_DELAY Register register, shown in Figure 7-15, can be used in all configu- PPI_DELAY rations except ITU-R 656 modes and GP modes with 0 frame syncs. It contains a count of how many cycles to delay after assertion of PPI_CLK before starting to read in or write out data.
Page 375: Ppi_Frame Register
Parallel Peripheral Interface Transfer Count Register (PPI_COUNT) 15 14 13 12 11 10 0xFFC0 1008 Reset = 0x0000 PPI_COUNT[15:0] In RX modes, holds one less than the number of samples to read in to the PPI per line. In TX modes, holds one less than the number of samples to write out through the PPI per line.
Page 376: Programming Examples
Programming Examples In ITU-R 656 modes, a frame start detect happens on the falling edge of F, the field indicator. This occurs at the start of field 1. In RX mode with 3 external frame syncs, a frame start detect refers to a condition where a assertion is followed by an assertion PPI_FS2...
Page 377 Parallel Peripheral Interface Listing 7-1. Configure DMA Registers config_dma: /* DMA0_START_ADDR */ R0.L = rx_buffer; R0.H = rx_buffer; P0.L = lo(DMA0_START_ADDR); P0.H = hi(DMA0_START_ADDR); [P0] = R0; /* DMA0_CONFIG */ R0.L = DI_EN | WNR; P0.L = lo(DMA0_CONFIG); P0.H = hi(DMA0_CONFIG); W[P0] = R0.L;...
Page 378 Programming Examples Listing 7-2. Configure PPI Registers config_ppi: /* PPI_CONTROL */ P0.L = lo(PPI_CONTROL); P0.H = hi(PPI_CONTROL); R0.L = 0x0004; W[P0] = R0.L; ssync; config_ppi.END: RTS; Listing 7-3. Enable DMA /* DMA0_CONFIG */ P0.L = lo(DMA0_CONFIG); P0.H = hi(DMA0_CONFIG); R0.L = W[P0]; bitset(R0,0);...
Page 379: Data Transfer Scenarios
Parallel Peripheral Interface Listing 7-5. Clear DMA Completion Interrupt /* DMA0_IRQ_STATUS */ P2.L = lo(DMA0_IRQ_STATUS); P2.H = hi(DMA0_IRQ_STATUS); R2.L = W[P2]; BITSET(R2,0); W[P2] = R2.L; ssync; Data Transfer Scenarios Figure 7-18 shows two possible ways to use the PPI to transfer in video. These diagrams are very generalized, and bandwidth calculations must be made only after factoring in the exact PPI mode and settings (for example, transfer field 1 only, transfer odd and even elements).
Page 380 Programming Examples DMA channel transfers data blocks between SDRAM and L1 memory for intermediate processing stages. Finally, the compressed video exits the processor via the SPORT. VIDEO DATA AND CONTROL VIDEO SPORT SOURCE MEMORY COMPRESSED VIDEO VIDEO SDRAM SOURCE MEMORY SPORT Figure 7-18.
Page 381: Overview
8 ETHERNET MAC This chapter describes the Ethernet Media Access Controller (MAC) peripheral for the ADSP-BF536 and ADSP-BF537 processors. Following an overview and list of key features is a description of operation and func- tional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples.
Page 382: Interface Overview
Interface Overview • Flexible address filtering • Flexible event detection for interrupt handling • Validation of IP and TCP (payload) checksum • Remote-wakeup Ethernet frames • Network-aware system power management The MAC is fully compliant to IEEE Std. 802.3-2002. Interface Overview Figure 8-1 illustrates the overall architecture of the Ethernet controller.
Page 383 Ethernet MAC CORE SYSTEM INTERFACE BLOCK (SIF) REGISTERS BLOCK (SIF_REG) TX FIFO RX FIFO MAC MANAGEMENT COUNTERS (MMC) ADDRESS CHECK BLOCK (ACH) MAC BLOCK POWER MANAGEMENT BLOCK (PMT) FLOW CONTROL MII MANAGEMENT MII/RMII PADS (MIM) PHYINT MDIO EXTERNAL PHY Figure 8-1. Ethernet MAC Block Diagram The Power Management (PMT) block adds support for wakeup frames and magic packet technology that allows waking up the processor from low power operating modes.
Page 384: External Interface
Interface Overview The MII Management (MIM) block handles all transactions to the control and status registers on the external PHY. External Interface Clocking The Ethernet MAC is clocked internally from on the processor. A SCLK buffered version of may be used to drive the external PHY via the CLKIN pin.
Page 385: Pins
Ethernet MAC Pins MII and RMII peripherals are multiplexed into the general-purpose ports, with port H and port J supporting this functionality. To use MII and RMII operations, set the register accordingly. See Chapter 14, PORTH_FER “General-Purpose Ports” for more information. The two MII and RMII signals (MDIO/MDC) in port J are not multiplexed, and are directly con- nected to pins Table 8-1...
Page 386: Internal Interface
Interface Overview Table 8-1. Ethernet MAC Pins (Cont’d) Pin Name RMII RMII Description Multiplexed Input/ Multiplexed Input/ Name Output Name Output PH10 MII RXD2 Ethernet MII receive D2 PH11 MII RXD3 Ethernet MII receive D3 PH12 MII RXDV Ethernet MII receive data valid PH13 Ethernet MII receive clock RXCLK...
Page 387: Power Management
Ethernet MAC Power Management The ADSP-BF536/ADSP-BF537 provides power management states which allow programming the MAC to wake the processor upon reception of specific Ethernet frames and/or upon selected events detected by the PHY. The MAC itself requires no additional power management interven- tion;...
Page 388 Description of Operation serial connection composed of the (management data clock) output signal and the (management data input/output) bidirectional data MDIO signal. See Figure 8-3 Figure 8-4. The MII management logical interface specifies: • A set of 16-bit device control/status registers within PHYs, includ- ing both required registers with standardized bit definitions as well as optional vendor-specified registers •...
Page 389 Ethernet MAC reduced preamble or increased clock rate. The features supported by the PHY may be determined at powerup by a MDIO read access (at default rates) of device capabilities in PHY status registers. IDLE PREAMBLE PHYAD REGAD DATA IDLE A A A A A R R R R R D D D D D D D D D D D D D D D D MDIO...
Page 390: Operation
Description of Operation Operation The following sections describe the detailed operation of the Ethernet MAC peripheral. MII Management Interface Operation The MAC peripheral performs MDIO-protocol transfers in response to register read/write commands issued by the Blackfin processor. Three reg- isters are provided to support MII management transfers: •...
Page 391: Receive Dma Operation
Ethernet MAC functions while station management transfers are in progress. Alterna- tively, the processor may determine the status of the transfer in progress by reading the bit in the register. STABUSY EMAC_STAADD Receive DMA Operation Data flow between the MAC and the Blackfin peripheral subsystem takes place via bidirectional descriptor based DMA.
Page 392 Description of Operation Receive DMA works with a queue or ring of DMA descriptor pairs struc- tured as data and status. • Data – The first descriptor in each pair points to a data buffer that is at least 1556 (0x614) bytes long and is 32-bit aligned. The descriptor field should be set to 0, because the MAC con- XCOUNT...
Page 393: Frame Reception And Filtering
Ethernet MAC • End of frame – At the end of the frame, the MAC issues a finish command to the DMA controller, causing it to advance to the next (status) descriptor. • Status – The MAC then transfers the frame status into the status buffer.
Page 394 Description of Operation The address filter is evaluated in the following sequence. Note that this sequence is in the same order as the related bits in the operating mode reg- ister, from LSB to MSB: , and . The first few filter decisions are additive, while the last two are subtractive.
Page 395 Ethernet MAC The frame filter is evaluated in the following sequence. Note that the frame filter is updated as each byte of data is received. The frame filter can change from true to false during a frame, for example, upon DMA over- run, but can never change from false back to true.
Page 396 Description of Operation Discarded Frames Frames that fail the address filter are discarded immediately after the desti- nation address is received, and neither their data nor their status values are written to memory via DMA. Frames that pass the address filter but fail the frame filter before 32 bytes are received are also discarded immedi- ately.
Page 397: Rx Automatic Pad Stripping
Ethernet MAC only those error-free unicast frames that exactly match the station MAC address. Set to accept all multicast addresses, or set and program the multicast hash table registers to accept only a sub- set of multicast addresses. • To accept all addresses, set and clear in the operat- ing mode register.
Page 398: Rx Dma Data Alignment
Description of Operation RX DMA Data Alignment If the bit in the MAC system control register is clear, the MAC RXDWA delivers the frame data via DMA to a 32-bit-aligned buffer in memory, including the Ethernet header and FCS. Because the Ethernet header is an odd number of 16-bit words long, this results in the frame payload being odd-aligned, which may be inconvenient for later processing.
Page 399: Rx Frame Status Buffer
Ethernet MAC are truncated by the MAC. The 1556-byte hardware limit accommodates the longest legal Ethernet frames (1518 bytes for untagged frames, or 1522 bytes for tagged 802.1Q frames) plus a small margin to accommo- date future standards extensions. The MAC does not support RX DMA data buffers composed of more than one descriptor.
Page 400: Rx Frame Status Classification
Description of Operation Table 8-3. Receive Status DMA Buffer Format (With IP Checksum) (Cont’d) Offset Size Description IP payload checksum RX frame status (Same format as the current RX frame status register) RX Frame Status Classification The RX frame status buffer and the RX current frame status register pro- vide a convenient classification of each received frame, representing the IEEE-802.3 “receive status”...
Page 401: Rx Ip Frame Checksum Calculation
Ethernet MAC Table 8-4. RX Receive Status Priority (Cont’d) Priority Bit Name IEEE receive Condition status Frame too Frame too long The frame size was more than the maxi- long mum allowable frame size (1518, 1522, or 1538 bytes for normal, VLAN1, or VLAN2 frames) Alignment Alignment error...
Page 402: Rx Dma Direction Errors
Description of Operation addition the property of being endian invariant, which makes it possible for software running on Blackfin’s little-endian architecture to adjust the sums without explicit byte swapping. See also RFC 1624 and its references. The checksum calculation hardware provides an enormous boost to TCP/IP throughput and bandwidth, but requires checksum corrections in software to properly adapt to the details of each packet protocol.
Page 403 Ethernet MAC In order to facilitate software debugging, the RX DMA channel guarantees that the last transfer to occur is the one with the direction error. On an error, usually the current frame is corrupted. All later frames are ignored until the error is cleared.
Page 404: Transmit Dma Operation
Description of Operation Transmit DMA Operation Figure 8-7 shows the transmit DMA operation. Active DMA Descriptor ActiveQueueEnd ActiveQueueHead DESCRIPTORS: XXXX STATUS BUFFERS: 0000 0000 DONE NOT DONE NOT DONE LENGTH LENGTH LENGTH DATA BUFFERS: DATA DATA DATA Figure 8-7. Ethernet MAC Transmit DMA Operation Transmit DMA normally works with a queue or ring of DMA descriptor pairs.
Page 405 Ethernet MAC transmission of its frame data is complete. Alternatively, status descriptors can be individually enabled to signal an interrupt when frame transmission is complete. The MAC and DMA operate on the active queue in this manner: • Start – The queue is activated by initializing the DMA register and then writing the register.
Page 406 Description of Operation then the MAC issues a restart command to the DMA controller to repeat the DMA of the current descriptor’s data buffer (if enabled by the bit). LCTRE • End of frame – At the end of the frame, the MAC issues a finish command to the DMA controller, causing it to advance to the next (status) descriptor.
Page 407: Flexible Descriptor Structure
Ethernet MAC Flexible Descriptor Structure The Blackfin processor’s DMA structure allows flexibility in the arrange- ment of TX frame data in memory. The frame data can be partitioned into segments, each with a separate DMA descriptor, which allows any of the first 88 bytes of DMA data (86 bytes of frame data) to reside in a separate data segment from the remainder of the frame.
Page 408: Late Collisions
Description of Operation In all cases, the TX DMA length word specifies the number of bytes to be transfered via DMA, excluding the TX DMA length word itself. Specifi- cally, when is set, the TX DMA length word includes the length of TXDWA the two pad bytes.
Page 409: Tx Frame Status Classification
Ethernet MAC If the bit is clear and a late collision is detected, the MAC issues a LCRTE finish command to the TX DMA controller, advancing the DMA channel to the status descriptor. The MAC then transfers the TX frame status to memory and advances to the next frame descriptor for data.
Page 410: Tx Dma Direction Errors
Description of Operation TX DMA Direction Errors The TX DMA channel halts immediately after any transfer that sets the bit in the register. This bit is set if a TX data or sta- TXDMAERR EMAC_SYSTAT tus DMA request is granted by the DMA channel, but the DMA channel is programmed to transfer in the wrong direction.
Page 411: Power Management
Ethernet MAC Power Management The Blackfin MAC can be programmed to trigger the following two types of power state transitions: 1. Wake from hibernate When the processor is in hibernate state (V powered off) or DDINT any higher state, a low level on the pin can wake the proces- PHYINT sor to the full on state (via...
Page 412 Description of Operation 2. Wake from sleep When the processor is in the sleep state (or any higher state), the Ethernet MAC can remain powered up and can wake the processor to the active or full on states upon signalling an Ethernet event interrupt.
Page 413: Ethernet Operation In The Sleep State
Ethernet MAC Ethernet Operation in the Sleep State When the ADSP-BF536/ADSP-BF537 is in the sleep state, the Ethernet MAC supports several levels of operation. • The MAC may be powered down, by clearing in the operating modes register. In this lowest-power state, the MAC’s internal clocks do not run, and the MAC neither transmits nor responds to received frames.
Page 414: Magic Packet Detection
Description of Operation This state is intended to be used with very restricted receive-frame filters, so that only certain specific frames are stored via DMA—perhaps only the frame(s) which caused the wakeup event itself. The transmit functionality permits the proces- sor to enqueue a list of final frame transmissions before going to sleep.
Page 415: Remote Wake-Up Filters
Ethernet MAC address fields). This byte pattern consists of 6 consecutive bytes of 0xFFs followed by sixteen consecutive repeats of the MAC address of the MAC which is targeted for wakeup. See Figure 8-10. Good Magic Packet frames exclude frame-too-short error, frame-too-long error, FCS error, Alignment error, and PHY error conditions.
Page 416 Description of Operation Each of the four filters sets a separate status bit ( – ) in the RWKS0 RWKS3 register upon detection of their programmed frame pat- EMAC_WKUP_CTL tern. The Ethernet event interrupt is asserted when any of these four status bits is set to 1;...
Page 417 Ethernet MAC 6. The 16-bit wakeup filter N pattern CRC field in the register specifies the 16-bit CRC hash value EMAC_WKUP_FFCRC0/1 expected for the wake-up pattern. Each filter has a separate 16-bit CRC state register which is independently updated as the frame is received. The CRC state for filter N is only updated when an enabled byte is received;...
Page 418: Ethernet Event Interrupts
Description of Operation The CRC-16 hash value for a sequence of bytes may be calculated serially, with each byte processed LSB-first. The initial value of the CRC state is 0xFFFF (all 1s). For each input bit, the LFSR is shifted left one position, and the bit shifted out is XORed with the new input bit.
Page 419 Ethernet MAC interrupt is signaled on peripheral interrupt ID 2 in the System Interrupt Controller (SIC), together with error conditions from a number of other peripherals. By default, peripheral interrupt ID 2 is mapped to IVG7 ETHERNET MAC DMA ERROR DMAR0 BLOCK DONE DMAR1 BLOCK DONE DMAR0 OVERFLOW...
Page 420 Description of Operation Ethernet MAC, the handler should read the Ethernet MAC system status register, as all of the MAC Ethernet event interrupt condition types are represented in that register. These conditions result in an Ethernet event interrupt: • PHYINT interrupt – Whenever the asynchronous pin is PHYINT asserted low, the...
Page 421 Ethernet MAC • TX frame status interrupt – The TX frame status interrupt condi- tion is signalled whenever the logical AND of the TX sticky frame status register and the TX frame status interrupt enable register is nonzero. This condition is cleared by writing 1s to all of the TX sticky frame status register bits that are enabled in the TX frame status interrupt enable register.
Page 422: Rx/Tx Frame Status Interrupt Operation
Description of Operation When the MAC DMA engine is disabled, all the MAC peripheral requests are routed directly into the interrupt controller. This can manifest itself at startup as spurious interrupts. The solution is to configure the system in such a way that the DMA controller is always enabled before the MAC peripheral.
Page 423: Startup And Shutdown
Ethernet MAC RX Frame Status Register Operation at Startup and Shutdown After the bit in the register is cleared, the RX current EMAC_OPMODE frame status register, the RX sticky frame status register, and the RX frame status interrupt enable register hold their last state. Of course, the two writable registers can still be written.
Page 424 Description of Operation conclusion of each frame. The counters may be read at any time, but may not be written. The counters can be reset to zero all at once by writing the bit to 1. RSTC The counters can be configured to be cleared individually after each read access if the bit is set to 1.
Page 425 Ethernet MAC MMC interrupt on the Ethernet event interrupt line when they pass half of the maximum counter value. Even if interrupt latency is large, this mechanism makes it unlikely that any counter data is lost to overrun. A recommended structure for the ISR for the MMC interrupt would be as follows.
Page 426: Programming Model
Programming Model was taken, then those interrupts are still correctly EMAC_MMC_TIRQS pending at the RTI; the interrupt handler is then re-entered and the remaining counter interrupts are handled in a second pass. Programming Model The following sections describe the Ethernet MAC programming model for a typical system.
Page 427: Multiplexing Scheme
Ethernet MAC Multiplexing Scheme The MII interface pins are multiplexed with GPIO pins on port H. To configure a pin on port H for Ethernet MAC functionality, the PORTH_FER bit corresponding to that pin must be set to 1. The MII management pins ( ) are available on port J.
Page 428: Configure Mac Registers
Programming Model • The wakeup frame events are controlled through the register. EMAC_WKUP_CTL • The TX DMA direction error detected and RX DMA direction error detected interrupts are non-maskable. Therefore, an interrupt service routine to handle them should always be installed. •...
Page 429 Ethernet MAC To perform a station management write transfer: 1. Initialize in the register. The frequency of the MDCDIV EMAC_SYSCTL MDC clock is . Thus SCLK / [ 2 * (MDCDIV + 1) ] . For typical 400ns MDCDIV ( SCLK_Freq / MDC_Freq )/2 - 1 (2.5MHz) MDC rate at , set SCLK = 125MHz...
Page 430: Configure Phy
Programming Model Configure PHY After the MII interface is configured, the PHY can be programmed with registers. Before configuration, the EMAC_STAADD EMAC_STADAT PHY is usually issued a soft reset. Depending of the capabilities of the spe- cific PHY device, the configurable options might include auto-negotiation, link speed, and whether the transfers are full-duplex or half-duplex.
Page 431: Receiving Data
Ethernet MAC Receiving Data In order to receive data, memory buffers must be allocated to construct a queue of DMA data and status descriptors. If the bit in RXDWA EMAC_SYSCTL is 0, then the first item in the receive frame header is the destination MAC address.
Page 432 Ethernet MAC Register Definitions Most registers require 32-bit accesses, but certain registers have only 16 or fewer functional bits and can be accessed with either 16-bit or 32-bit MMR accesses. Table 8-9 shows the functions of the MAC registers. MMC counter regis- ters are found in Table 8-10 on page 8-54.
Page 433 Ethernet MAC Table 8-9. MAC Register Mapping (Cont’d) Register Name Function Notes EMAC_WKUP_FFMSK1 MAC wakeup frame 1 byte mask EMAC_WKUP_FFMSK2 MAC wakeup frame 2 byte mask EMAC_WKUP_FFMSK3 MAC wakeup frame 3 byte mask EMAC_WKUP_FFCMD MAC wakeup frame filter commands EMAC_WKUP_FFOFF MAC wakeup frame filter offsets EMAC_WKUP_FFCRC0...
Page 434 Ethernet MAC Register Definitions Table 8-9. MAC Register Mapping (Cont’d) Register Name Function Notes EMAC_MMC_RIRQS Ethernet MAC MMC RX interrupt status EMAC_MMC_RIRQE Ethernet MAC MMC RX interrupt enable EMAC_MMC_TIRQS Ethernet MAC MMC TX interrupt status EMAC_MMC_TIRQE Ethernet MAC MMC TX interrupt enable MAC Management Counter Register Group EMAC_MMC_CTL...
Page 435 Ethernet MAC Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 3104 EMAC_RXC_FCS Holds a count of receive frames that are (FrameCheckSequenceErrors) an integral number of octets in length 30.3.1.1.6 and do not pass the FCS check. This does not include frames received with frame-too-long or frame-too-short (frame fragment) errors.
Page 436 Ethernet MAC Register Definitions Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 3114 EMAC_RXC_UNICST Holds a count of frames counted by the (UnicastFramesReceivedOK) EMAC_RXC_OK register that are not No IEEE reference counted by the EMAC_RXC_MULTI or the EMAC_RXC_BROAD register.
Page 437 Ethernet MAC Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 3120 EMAC_RXC_LNERRI Holds a count of frames with a (InRangeLengthErrors) length/type field value between the 30.3.1.1.23 minimum unpadded MAC client data size and the maximum allowed MAC client data size, inclusive, that does not match the number of MAC client data...
Page 438 Ethernet MAC Register Definitions Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 312C EMAC_RXC_MACCTL Holds a count of MAC control frames (MACControlFramesReceived) passed by the MAC sublayer to the 30.3.3.4 MAC control sublayer.
Page 439 Ethernet MAC Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 3138 EMAC_RXC_ALLFRM Holds a count of all frames or frame (FramesReceivedAll) fragments detected by the Ethernet No IEEE reference MAC, regardless of errors and regard- less of address, except for DMA over- run frames.
Page 440 Ethernet MAC Register Definitions Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 3154 EMAC_RXC_LT512 Holds a count of all good frames (with (FramesLen256_511Received) status receiveOK) that have a length No IEEE reference between 256 and 511 bytes, inclusive.
Page 441 Ethernet MAC Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 318C EMAC_TXC_OCTET Holds a count of data and padding (OctetsTransmittedOK) octets in frames that are successfully 30.3.1.1.8 transmitted. This counter is incre- mented when the transmit status is reported as transmit OK.
Page 442 Ethernet MAC Register Definitions Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 319C EMAC_TXC_DMAUND Holds a count of frames that would (FramesLostDueToIntMACXmit otherwise be transmitted by the sta- Error) tion, but could not be sent due to an 30.3.1.1.12 internal MAC sublayer transmit error.
Page 443: Control-Status Register Group
Ethernet MAC Table 8-10. MAC Management Counter Registers (Cont’d) MMR Address Register Name Description (IEEE Name) IEEE 802.3 Reference 0xFFC0 31B4 EMAC_TXC_MACCTL Holds a count of MAC control frames (MACControlFramesTransmitted) passed to the MAC sublayer for trans- 30.3.3.3 mission. Note this counter is incre- mented only when a MAC pause frame is generated by writing to the EMAC_FLC register.
Page 444: Emac_Opmode Register
Ethernet MAC Register Definitions EMAC_OPMODE Register register, shown in Figure 8-13, controls the address fil- EMAC_OPMODE tering and collision response characteristics of the Ethernet controller in both the RX and TX modes. MAC Operating Mode Register (EMAC_OPMODE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 3000 Reset = 0x0000 0000 DRO (Disable Receive...
Page 445 Ethernet MAC [1] Receive own frames disabled. [0] Receive own frames enabled. • Internal loopback enable ( When internal loopback is enabled, the frames transmitted by the MAC are internally redirected to the receive MAC port. The exter- nal MII port is inactive. The RX pins are ignored and the TX pins are set to TXEN = 0 TXD = 1111...
Page 446 Ethernet MAC Register Definitions • RMII mode ( RMII This bit is used to select which interface, RMII or MII, is used by the MAC to transfer data to and from the external PHY. Note that MII and RMII modes use slightly different sets of package pins. Program different values into the register accordingly.
Page 447 Ethernet MAC [10] The number of bits is 4 and the maximum back-off time is 15 slots. [11] The number of bits is 1 and the maximum back-off time is 1 slot (aggressive) • Deferral check ( In half-duplex operation, a frame whose transmission defers to incoming traffic for longer than two maximum-length frame times is considered to have been excessively deferred.
Page 448 Ethernet MAC Register Definitions • Transmitter enable ( The MAC transmitter is reset when is 0. A rising (0 to 1) transi- tion on causes the TX current frame status register and the TX sticky frame status register to be reset. Note in RMII mode, only one reference clock ( ) is used, and it belongs to the transmit- REFCLK...
Page 449 Ethernet MAC • Inverse filtering ( [1] Removes the MAC address programmed in the EMAC_ADDRHI registers from the set of addresses passed by the EMAC_ADDRLO address filter, overriding (promiscuous) and (hash unicast) modes. The effect is to block reception of a specific destination address.
Page 450: Emac_Addrlo Register
Ethernet MAC Register Definitions • Hash filter unicast addresses ( [1] Adds unicast addresses that match the hash table to the set of addresses passed by the address filter. [0] Does not add unicast addresses that match the hash table to the set of addresses passed by the address filter.
Page 451: Emac_Addrhi Register
Ethernet MAC For example, the address (where 00 is transferred first 00:12:34:56:78:9A and 9A is transferred last) would be programmed as: EMAC_ADDRLO = 0x56341200 EMAC_ADDRHI = 0x00009A78 MAC Address Low Register (EMAC_ADDRLO) R/W, except cannot be written if RX or TX is enabled in the EMAC_OPMODE register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 3004 Reset = 0xFFFF FFFF...
Page 452: Emac_Hashlo And Emac_Hashhi Registers
Ethernet MAC Register Definitions EMAC_HASHLO and EMAC_HASHHI Registers register holds the values for bins 31–0 of the multicast EMAC_HASHLO hash table. The register holds the values for bins 63–32 of EMAC_HASHHI the multicast hash table. See Figure 8-16 Figure 8-17. The 64-bit multicast table is used for multicast frame address filtering.
Page 453 Ethernet MAC The 32-bit CRC register is initialized to all 1s. Then each input bit is pro- cessed as follows: first, the register is shifted left one place, shifting in a zero and shifting out the former MSB. The bit just shifted out is XORed with the current input bit, yielding the feedback bit.
Page 454 Ethernet MAC Register Definitions MAC Multicast Hash Table Low Register (EMAC_HASHLO) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 300C Bin 31 Bin 16 Bin 30 Bin 17 Bin 29 Bin 18 Bin 28...
Page 455 Ethernet MAC MAC Multicast Hash Table High Register (EMAC_HASHHI) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3010 Bin 63 Bin 48 Bin 62 Bin 49 Bin 61 Bin 50 Bin 60 Bin 51...
Page 456: Emac_Staadd Register
Ethernet MAC Register Definitions EMAC_STAADD Register register, shown in Figure 8-18, controls the transactions EMAC_STAADD between the MII management (MIM) block and the registers on the exter- nal PHY. These transactions are used to appropriately configure the PHY and monitor its performance. MAC Station Management Address Register (EMAC_STAADD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 3014...
Page 457 Ethernet MAC • Disable preamble generation ( STADISPRE [1] Preamble generation (32 ones) for station management trans- fers disabled. [0] Preamble generation for station management transfers not disabled. • Station management operation code ( STAOP [1] Write. [0] Read. • STA busy status ( STABUSY This bit should be set by the application software in order to ini- tiate a station management register access.
Page 458: Emac_Stadat Register
Ethernet MAC Register Definitions EMAC_STADAT Register register, shown in Figure 8-19, contains either the data EMAC_STADAT to be written to the PHY register specified in the MAC station manage- ment address register, or the data read from the PHY register whose address is specified in the MAC station management address register.
Page 459 Ethernet MAC MAC Flow Control Register (EMAC_FLC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 301C Reset = 0x0000 0000 FLCPAUSE[15:0] (Pause Time) 15 14 13 12 11 10 BKPRSEN (Enable Backpressure) FLCBUSY (Flow Control Busy Status)
Page 460: Emac_Vlan1 And Emac_Vlan2 Registers
Ethernet MAC Register Definitions [1] Pass control frames. [0] Do not pass control frames. • Flow control enable ( FLCE When set, this bit enables interpretation of MAC control pause frames that are received without errors. [1] Flow control enabled. [0] Flow control not enabled.
Page 461: Emac_Wkup_Ctl Register
Ethernet MAC MAC VLAN1 Tag Register (EMAC_VLAN1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 FFFF 0xFFC0 3020 15 14 13 12 11 10 VLAN1TAG[15:0] (Length/Type Tag) Figure 8-21. MAC VLAN1 Tag Register MAC VLAN2 Tag Register (EMAC_VLAN2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 FFFF...
Page 462 Ethernet MAC Register Definitions MAC Wakeup Frame Control and Status Register (EMAC_WKUP_CTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 302C Reset = 0x0000 0000 15 14 13 12 11 10 CAPWKFRM (Capture RWKS[3:0] (Wakeup Frame Wakeup Frames)
Page 463 Ethernet MAC • Global unicast wake enable ( GUWKE When set, configures the MAC to wake up from the power-down mode on receipt of a global unicast frame. Such a frame has the MAC address [1:0] bits cleared. [1] Global unicast wake enabled. [0] Global unicast wake not enabled.
Page 464: Emac_Wkup_Ffmsk2, And Emac_Wkup_Ffmsk3 Registers
Ethernet MAC Register Definitions EMAC_WKUP_FFMSK0, EMAC_WKUP_FFMSK1, EMAC_WKUP_FFMSK2, and EMAC_WKUP_FFMSK3 Registers , and EMAC_WKUP_FFMSK0 EMAC_WKUP_FFMSK1 EMAC_WKUP_FFMSK2 registers (see Figure 8-24 through Figure 8-27) are a EMAC_WKUP_FFMSK3 part of the mechanism used to select which bytes in a received frame are used for CRC computation. Each bit in these registers functions as a byte enable.
Page 465 Ethernet MAC MAC Wakeup Frame0 Byte Mask Register (EMAC_WKUP_FFMSK0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3030 Byte Enable 31 Byte Enable 16 Byte Enable 30 Byte Enable 17 Byte Enable 29 Byte Enable 18...
Page 466 Ethernet MAC Register Definitions MAC Wakeup Frame1 Byte Mask Register (EMAC_WKUP_FFMSK1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3034 Byte Enable 31 Byte Enable 16 Byte Enable 30 Byte Enable 17 Byte Enable 29 Byte Enable 18...
Page 467 Ethernet MAC MAC Wakeup Frame2 Byte Mask Register (EMAC_WKUP_FFMSK2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3038 Byte Enable 31 Byte Enable 16 Byte Enable 30 Byte Enable 17 Byte Enable 29 Byte Enable 18...
Page 468 Ethernet MAC Register Definitions MAC Wakeup Frame3 Byte Mask Register (EMAC_WKUP_FFMSK3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 303C Byte Enable 31 Byte Enable 16 Byte Enable 30 Byte Enable 17 Byte Enable 29 Byte Enable 18...
Page 469: Emac_Wkup_Ffcmd Register
Ethernet MAC EMAC_WKUP_FFCMD Register register, shown in Figure 8-28, regulates which of EMAC_WKUP_FFCMD the four frame filter registers are enabled and if so, whether they are con- figured for unicast or multicast address filtering. MAC Wakeup Frame Filter Commands Register (EMAC_WKUP_FFCMD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 3040 Reset = 0x0000 0000...
Page 470 Ethernet MAC Register Definitions • Wakeup filter 2 address type [1] Multicast [0] Unicast • Enable wakeup filter 2 [1] Wakeup filter 2 enabled. [0] Wakeup filter 2 not enabled. • Wakeup filter 1 address type [1] Multicast [0] Unicast •...
Page 471: Emac_Wkup_Ffoff Register
Ethernet MAC EMAC_WKUP_FFOFF Register register, shown in Figure 8-29, contains the byte EMAC_WKUP_FFOFF offsets for CRC computation to be performed on potential wakeup frames. Ethernet MAC Wakeup Frame Filter Offsets Register (EMAC_WKUP_FFOFF) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3044 Wakeup Filter 2...
Page 472: Emac_Wkup_Ffcrc0 And Emac_Wkup_Ffcrc1 Registers
Ethernet MAC Register Definitions EMAC_WKUP_FFCRC0 and EMAC_WKUP_FFCRC1 Registers register, shown in Figure 8-30, and the EMAC_WKUP_FFCRC0 register, shown in Figure 8-31, should be loaded with EMAC_WKUP_FFCRC1 the results of the CRC computations for the relevant wakeup frame bytes. “Remote Wake-up Filters” on page 8-35.
Page 473: System Interface Register Group
Ethernet MAC System Interface Register Group The SIF block registers control and monitor the MAC’s interactions with the Blackfin processor peripheral subsystem and the external PHY. The SIF block has several frame status registers whose bit descriptions can be found in “Ethernet MAC Frame Status Registers”...
Page 474 Ethernet MAC Register Definitions Additional information for the register bits includes: EMAC_SYSCTL • SCLK:MDC clock divisor ( MDCDIV[5:0] This field contains the clock divisor that determines the ratio between the Blackfin system clock ( ) and the MAC data clock SCLK (MDC).
Page 475: Emac_Systat Register
Ethernet MAC EMAC_SYSTAT Register register, shown in Figure 8-33, contains a range of inter- EMAC_SYSTAT rupt status bits that signal the occurrence of significant Ethernet events to the application. Detailed descriptions of the functionality can be found in the section entitled “Ethernet Event Interrupts”...
Page 476 Ethernet MAC Register Definitions • TX DMA direction error status ( TXDMAERR This bit is set if a TX data or status DMA request is granted by the DMA channel with transfer in the wrong direction. Data should be memory-read, status should be memory-write. This interrupt is non-maskable in the Ethernet MAC.
Page 477: Ethernet Mac Frame Status Registers
Ethernet MAC • MMC counter interrupt status ( MMCINT To clear this bit, write 1 to the EMAC_MMC_RIRQS EMAC_MMC_TIRQS register. [1] MMC counter interrupt has occurred. [0] MMC counter interrupt has not occurred. • PHYINT interrupt status ( PHYINT [1] PHYINT interrupt has occurred. [0] PHYINT interrupt has not occurred.
Page 478 Ethernet MAC Register Definitions Note if the (pass bad frames) bit is 0, then delivery via DMA of frames with status bits 14 through 18 or 20 is cancelled. The DMA buffer is reused for the next frame. If the (promiscuous) bit is 0, then frames with bit 19 set are not delivered (the DMA is never initiated).
Page 479 Ethernet MAC (receive all) control bit is 0, then the only frames delivered by DMA are the frames whose receive frame accepted status bit is 1. [0] Receive frame not accepted. • VLAN2 frame ( RX_VLAN2 [1] The frame is a valid tagged frame with a length/type field matching the VLAN2 tag register, and with status of receiveOK.
Page 480 Ethernet MAC Register Definitions • Control frame ( RX_CTL [1] The frame is a valid MAC control frame in full duplex mode with status of receiveOK, with a length/type field equal to MAC_Control, 88-08, with length of 64 bytes, and with a MAC control opcode field equal to the pause opcode (00-01).
Page 481 Ethernet MAC • DMA overrun ( RX_DMAO [1] The received frame was truncated due to failure of the FIFO/DMA channel to continuously store data during DMA transfer to memory. [0] No DMA overrun. • Address filter failed ( RX_ADDR [1] The destination address did not pass the address filters specified by the station MAC address, the multicast hash registers, and the filter modes in the operating modes register.
Page 482 Ethernet MAC Register Definitions • Alignment error ( RX_ALIGN [1] The frame ended with a partial octet and failed RCS validation, but had no frame too long error. [0] No alignment error. • Frame too long ( RX_LONG [1] The number of octets received is greater than the maximum Ethernet frame size.
Page 483: Emac_Rx_Stky Register
Ethernet MAC • Frame length ( RX_FRLEN The number of bytes in the frame. If the bit is set, the pad ASTP and FCS are not included in the length. EMAC_RX_STKY Register register, shown in Figure 8-35, accumulates state across EMAC_RX_STKY multiple frames, unless software clears it after every frame.
Page 484 Ethernet MAC Register Definitions Additional information for the register bits includes: EMAC_RX_STKY • Receive frames passed frame filter ( RX_ACCEPT [1] At least one receive frame passed the frame filter. [0] No receive frames passed the frame filter. • VLAN2 frames detected ( RX_VLAN2 [1] At least one VLAN2 frame was detected.
Page 485 Ethernet MAC • Multicast frames detected ( RX_MULTI [1] At least one multicast frame was detected. [0] No multicast frames were detected. • Out of range length fields detected ( RX_RANGE [1] At least one out of range length field was detected. [0] No out of range length fields were detected.
Page 486 Ethernet MAC Register Definitions • Length errors detected ( RX_LEN [1] At least one length error was detected. [0] No length errors were detected. • Frame CRC errors detected ( RX_CRC [1] At least one CRC error was detected. [0] No frame CRC errors were detected. •...
Page 487: Emac_Rx_Irqe Register
Ethernet MAC EMAC_RX_IRQE Register register, shown in Figure 8-36, enables the frame status EMAC_RX_IRQE interrupts. Ethernet MAC RX Frame Status Interrupt Enable Register (EMAC_RX_IRQE) For all bits, 1 = Interrupt enabled, 0 = Interrupt not enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 3070 Reset = 0x0000 0000 RX_CRC (Frame CRC Error...
Page 488: Emac_Tx_Stat Register
Ethernet MAC Register Definitions EMAC_TX_STAT Register register, shown in Figure 8-37, tells the status of the EMAC_TX_STAT most recently completed transmit frame, including type of error for cases where an error occurred. When the transmit complete bit is set, exactly one of bits 2, 3, 4, 13, or 14 is 1.
Page 489 Ethernet MAC • Late collision observed ( TX_RETRY [1] A late collision occurred, but the frame transmission was suc- cessful after retry. [0] No late collision occurred. • Loss of carrier ( TX_LOSS [1] The carrier sense transitioned from asserted to deasserted at some time during the frame transmission.
Page 490 Ethernet MAC Register Definitions • Collision count ( TX_CCNT This field contains the number of collisions that occurred during frame transmission. • TX broadcast, TX multicast ( TX_BROAD, TX_MULTI [1 1] Illegal [1 0] Group address [0 1] Broadcast address [0 0] Unicast address •...
Page 491 Ethernet MAC • Late collision error ( TX_LATE [1] Frame transmission failed because a collision occurred after the end of the collision window (512 bit times) and the bit was LCRTE clear, disabling frame transmission retry. [0] No late collision error. •...
Page 492: Emac_Tx_Stky Register
Ethernet MAC Register Definitions EMAC_TX_STKY Register register, shown in Figure 8-38, accumulates state across EMAC_TX_STKY multiple frames, unless software clears it after every frame. Ethernet MAC TX Sticky Frame Status Register (EMAC_TX_STKY) All bits in this register are W1C. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3078 15 14 13 12 11 10...
Page 493 Ethernet MAC • No carrier detected ( TX_CRS [1] At least one occasion of no carrier was detected. [0] No instances of no carrier were detected. • Frame deferrals detected ( TX_DEFER [1] At least one frame deferral was detected. [0] No frame deferrals were detected.
Page 494: Emac_Tx_Irqe Register
Ethernet MAC Register Definitions • Frames transmitted OK ( TX_OK This bit can be used to generate an interrupt at the completion of each TX frame. [1] At least one frame has been transmitted OK. [0] No good frames have been transmitted. •...
Page 495: Emac_Mmc_Rirqs Register
Ethernet MAC EMAC_MMC_RIRQS Register register, shown in Figure 8-40, indicates which of EMAC_MMC_RIRQS the receive MAC management counters have incremented past one-half of maximum range. Each bit is set from 0 to 1 when the corresponding counter increments from a value less than 0x8000 0000 to a value greater than or equal to 0x8000 0000 (regardless of the state of the interrupt enable register).
Page 496 Ethernet MAC Register Definitions Ethernet MAC MMC RX Interrupt Status Register (EMAC_MMC_RIRQS) All bits are W1C. For all bits, 1 = Interrupt occurred, 0 = Interrupt did not occur. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3084 RX_TYPED_CNT (Typed...
Page 497: Emac_Mmc_Rirqe Register
Ethernet MAC EMAC_MMC_RIRQE Register register, shown in Figure 8-41, indicates which of EMAC_MMC_RIRQE the receive MAC management counters are enabled to signal an MMCINT interrupt when they increment past one-half of maximum range. If a given counter’s interrupt is not enabled, and that counter passes 0x8000 0000, then the counter’s interrupt status bit is set to 1 but this does not cause the interrupt to be signalled.
Page 498 Ethernet MAC Register Definitions Ethernet MAC MMC RX Interrupt Enable Register (EMAC_MMC_RIRQE) For all bits, 1 = Interrupt enabled, 0 = Interrupt not enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3088 RX_TYPED_CNT (Typed...
Page 499: Emac_Mmc_Tirqs Register
Ethernet MAC EMAC_MMC_TIRQS Register register, shown in Figure 8-42, indicates which of EMAC_MMC_TIRQS the transmit MAC management counters have incremented past one-half of maximum range. Each bit is set from 0 to 1 when the corresponding counter increments from a value less than 0x8000 0000 to a value greater than or equal to 0x8000 0000 (regardless of the state of the interrupt enable register).
Page 500 Ethernet MAC Register Definitions Ethernet MAC MMC TX Interrupt Status Register (EMAC_MMC_TIRQS) All bits are W1C. For all bits, 1 = Interrupt occurred, 0 = Interrupt did not occur. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 308C TX_EQ64_CNT (Frames...
Page 501: Emac_Mmc_Tirqe Register
Ethernet MAC EMAC_MMC_TIRQE Register register, shown in Figure 8-43, indicates which of EMAC_MMC_TIRQE the transmit MAC management counters are enabled to signal an MMCINT interrupt when they increment past one-half of maximum range. If a given counter’s interrupt is not enabled, and that counter passes 0x8000 0000, then the counter’s interrupt status bit is set to 1 but this does not cause the interrupt to be signalled.
Page 502 Ethernet MAC Register Definitions Ethernet MAC MMC TX Interrupt Enable Register (EMAC_MMC_TIRQE) For all bits, 1 = Interrupt enabled, 0 = Interrupt not enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 3090 TX_EQ64_CNT (Frames...
Page 503: Mac Management Counter Registers
Ethernet MAC MAC Management Counter Registers The MAC Management Counter (MMC) block register group consists of a number of 32-bit unsigned counter registers that gather statistical data regarding the operation of the MAC. The MAC management counter reg- isters update automatically at the completion of frame transmit and receive, whenever the bit in the MMC control register is set.
Page 504: Emac_Mmc_Ctl Register
Ethernet MAC Register Definitions EMAC_MMC_CTL Register register, shown in Figure 8-44, is used to globally con- EMAC_MMC_CTL figure all MMC counter registers. MAC Management Counters Control Register (EMAC_MMC_CTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 3080 Reset = 0x0000 000A 15 14 13 12 11 10...
Page 505: Programming Examples
Ethernet MAC • Counter clear-on-read mode ( CCOR [1] Counters are in clear-on-read mode. The contents of each counter is reset each time it is read by the application. [0] Counters are not in clear-on-read mode. Reads do not affect counter contents.
Page 506: Ethernet Structures
Programming Examples of C structures. Also provided are code listings that describe accessing an external PHY via the station management (MIM) block. All macros which are not explained in this section can be found in the cdefBF537.h header files of VisualDSP++. defBF537.h The code examples in this section (Listing 8-1...
Page 507 Ethernet MAC u16 b_DMA2D:1; /* 4 DMA mode */ u16 b_RESTART:1; /* 5 Retain FIFO */ u16 b_DI_SEL:1; /* 6 Data interrupt timing select */ u16 b_DI_EN:1; /* 7 Data interrupt enabled */ u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */ u16 b_FLOW:3;...
Page 508 Programming Examples Listing 8-4. Ethernet Frame Buffer typedef struct adi_ether_frame_buffer { NoBytes; /* the no. of following bytes */ Dest[6]; /* destination MAC address */ Srce[6]; /* source MAC address */ LTfield; /* length/type field */ Data[0]; /* payload bytes */ } ADI_ETHER_FRAME_BUFFER;...
Page 509: Mac Address Setup
Ethernet MAC struct adi_ether_buffer *pNext; /* next buffer */ struct adi_ether_buffer *pPrev; /* prev buffer */ IPHdrChksum; /* the IP header checksum */ IPPayloadChksum; /* the IP header and payload checksum */ StatusWord; /* the frame status word */ } ADI_ETHER_BUFFER; MAC Address Setup Write in the initialization routine of the...
Page 510: Phy Control Routines
Programming Examples PHY Control Routines register provides the option of either polling the EMAC_STAAD STABUSY bit or getting an interrupt during each MIM block access. The function in Listing 8-7 polls the bit and should be placed after each read or STABUSY write command to the PHY register.
Page 511 Ethernet MAC SET_REGAD(RegAddr) |\ STAOP | STABUSY; The data in the register is immediately shifted out after a write to STADAT register. See Figure 8-4 on page 8-9. STAADD The function in Listing 8-9 shows how PHY data is read over the MIM function block of the MAC.
Page 512 Programming Examples A complete PHY initialization also requires the initialization of the station management clock, which is described in detail in the section “MII Sta- tion Management” on page 8-48. The three PHY functions included in this section (write, read, and poll) and the initialization routine of the sta- tion management clock are the minimum requirements for setup and control of any PHYs.
Page 513: Overview
9 CAN MODULE This chapter describes the Controller Area Network (CAN) module. Fol- lowing an overview and a list of key features is a description of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Familiarity with the CAN stan- dard is assumed.
Page 514: Interface Overview
Interface Overview The CAN module is a low bit rate serial interface intended for use in applications where bit rates are typically up to 1Mbit/s. The CAN proto- col incorporates a data CRC check, message error tracking and fault node confinement as means to improve network reliability to the level required for control applications.
Page 515 CAN Module BLACKFIN SIC CONTROLLER CANx INTERRUPT GLOBAL INTERRUPT FLAG GLOBAL INTERRUPT MASK GLOBAL INTERRUPT STATUS ERROR COUNTERS ERROR STATUS ERROR WARNING MAILBOX INTERRUPT MASK 1 MAILBOX INTERRUPT TRANSMIT 1 MAILBOX INTERRUPT MASK 2 MAILBOX INTERRUPT RECEIVE 1 MAILBOX INTERRUPT TRANSMIT 2 OVERWRITE PROTECTION/SINGLE SHOT 1 AILBOX INTERRUPT RECEIVE 2 COUNTER...
Page 516: Can Mailbox Area
Interface Overview CAN Mailbox Area The full-CAN controller features 32 message buffers, which are called mailboxes. Eight mailboxes are dedicated for message transmission, eight are for reception, and 16 are programmable in direction. Accordingly, the CAN module architecture is based around a 32-entry mailbox RAM. The mailbox is accessed sequentially by the CAN serial interface or the Black- fin core.
Page 517 CAN Module The CAN mailbox identification ( ) register pair includes: CAN_MBxx_ID0 • The 29 bit identifier (base part plus extended part BASEID EXTID_LO/HI • The acceptance mask enable bit ( • The remote transmission request bit ( • The identifier extension bit ( Do not write to the identifier of a message object while the mailbox is enabled for the CAN module (the corresponding bit in CAN_MCx...
Page 518: Can Mailbox Control
Interface Overview are reused as acceptance code ( ) for the data field filter- CAN_MBxx_ID0 ing. For more details, see “Receive Operation” on page 9-15 of this chapter. CAN Mailbox Control Mailbox control MMRs function as control and status registers for the 32 mailboxes.
Page 519: Can Protocol Basics
CAN Module • (transmit request reset registers) CAN_TRR1 CAN_TRR2 • (receive message pending registers) CAN_RMP1 CAN_RMP2 • (receive message lost registers) CAN_RML1 CAN_RML2 • (remote frame handling registers) CAN_RFH1 CAN_RFH2 • (overwrite protection/single shot CAN_OPSS1 CAN_OPSS2 transmission registers) • (mailbox interrupt mask registers) CAN_MBIM1 CAN_MBIM2 •...
Page 520 Interface Overview Each CAN node then begins transmitting its message starting with the message ID. While transmitting, the CAN controller samples the CANRX pin to verify that the logic level being driven is the value it just placed on pin. This is where the names for the logic levels apply. If a trans- CANTX mitting node places a recessive ‘1’...
Page 521: Can Operation
CAN Module The next field of interest is the . When set, it indicates that the mes- sage is an extended frame with a 29-bit identifier instead of an 11-bit identifier. In an extended frame, the first part of the message resembles Figure 9-6.
Page 522 CAN Operation register. Although the field can be set to any value, it is rec- CAN_CLOCK ommended that the value be greater than or equal to 4, as restrictions apply to the bit timing configuration when is less than 4. register defines the TQ value, and multiple time quanta CAN_CLOCK make up the duration of a CAN bit on the bus.
Page 523 CAN Module The Blackfin CAN module does not distinguish between the propagation segment and the phase segment 1 as defined by the standard. The TSEG1 value is intended to cover both of them. The value represents the TSEG2 phase segment 2. If the CAN module detects a signal edge outside the synchronization seg- ment, it can automatically move the sampling point such that the CAN bit is still handled properly.
Page 524: Transmit Operation
CAN Operation processor reset or hibernate, enter configuration mode by setting the bit in the master control ( ) register and poll the global status CAN_CONTROL ) register until the bit is set. CAN_STATUS If the field of the register is programmed to ‘0,’ TSEG1 CAN_TIMING the module doesn’t leave the configuration mode.
Page 525: Retransmission
CAN Module Multiple bits can be set simultaneously by software, and these CAN_TRSx bits are reset after either a successful or an aborted transmission. The TRSn bits can also be set by the CAN hardware when using the auto-transmit mode of the universal counter, when a message loses arbitration and the single-shot bit is not set ( ), or in the event of a OPSSn...
Page 526 CAN Operation AT LEAST 1 BIT SET IN CAN_TRSx REGISTERS STARTING WITH MAILBOX 31, FIND HIGHEST SET TRSn BIT PLACE MESSAGE n IN TEMPORARY TRANSMIT BUFFER MESSAGE ABORTED? CLEAR TRSn CLEAR TRSn AND REPORT AND REPORT TRANSMIT ABORT ERROR SUCCESSFUL EXIT EXIT Figure 9-8.
Page 527: Single Shot Transmission
CAN Module Single Shot Transmission If the single shot transmission feature is used ( ), the OPSSn CAN_OPSSx corresponding bit is cleared after the message is successfully sent or if TRSn the transmission is aborted due to a lost arbitration or an error frame on the CAN bus line.
Page 528 CAN Operation Each incoming data frame is compared to all identifiers stored in active receive mailboxes ( ) and to all active transmit mail- boxes with the remote frame handling feature enabled ( RFHn CAN_RFHx The message identifier of the received message, along with the identifier extension ( ) and remote transmission request ( ) bits, are compared...
Page 529 CAN Module Figure 9-9 illustrates the decision tree of the receive logic when processing the individual mailboxes. FROM MESSAGE RECEIVER/PREVIOUS MAILBOX MAILBOX NEXT MAILBOX ENABLED? COMPARE COMPARE ALL MASKED AME? BITS BITS ONLY NEXT MAILBOX MATCH? TRANSMIT RECEIVE MAILBOX DIRECTION? REMOTE MAILBOX NEXT MAILBOX...
Page 530: Data Acceptance Filter
CAN Operation interrupt status register ( ). If , the next mail- RMLIS CAN_GIS OPSSn boxes are checked for another matching identifier. If no match is found, the message is discarded and the next message is checked. If a receive mailbox is disabled, an ongoing receive message for that mailbox is lost even if a second mailbox is configured to receive the same identifier.
Page 531: Remote Frame Handling
CAN Module Remote Frame Handling Automatic handling of remote frames can be enabled/disabled by setting/ clearing the corresponding bit in the remote frame handling registers CAN_RFHx Remote frames are data frames with no data field and the bit set. The data length code of the data frame is equal to the of the corresponding remote frame.
Page 532: Time Stamps
CAN Operation Upon programming the universal counter to watchdog mode (set ), the counter in the register is UCCNF[3:0] CAN_UCCNF CAN_UCCNT loaded with the predefined value contained in the CAN universal counter reload/capture register ( ). This counter then decrements at the CAN_UCRC CAN bit rate.
Page 533: Temporarily Disabling Mailboxes
CAN Module If the mailbox is configured for automatic remote frame handling, the time stamp value is written for transmission of a data frame (mailbox con- figured as transmit) or the reception of the requested data frame (mailbox configured as receive). The counter can be cleared (set bit to 1) or disabled (set bit to 0)
Page 534: Functional Operation
Functional Operation If a mailbox is configured as “transmit” ( ) and is set, the con- tent of the data field of that mailbox can be updated. If there is an incoming remote request frame while the mailbox is temporarily disabled, the corresponding transmit request set bit ( ) is set by the internal TRSn...
Page 535: Can Interrupts
CAN Module CAN Interrupts The CAN module provides three independent interrupts: two mailbox interrupts (mailbox receive interrupt and mailbox transmit inter- MBRIRQ rupt ) and the global interrupt . The values of these three MBTIRQ GIRQ interrupts can also be read back in the interrupt status registers. Mailbox Interrupts Each of the 32 mailboxes in the CAN module may generate a receive or transmit interrupt, depending on the mailbox configuration.
Page 536: Global Interrupt
Functional Operation Global Interrupt The global interrupt logic is implemented with three registers—the global interrupt mask register ( ), where each interrupt source can be CAN_GIM enabled or disabled separately; the global interrupt status register ); and the global interrupt flag register ( ).
Page 537 CAN Module • Receive message lost interrupt ( RMLIM RMLIS RMLIF A message has been received for a mailbox that currently contains unread data. At least one bit in the receive message lost register ) is set. If the bit in (and ) is reset and CAN_RMLx...
Page 538: Event Counter
Functional Operation • Error-Passive interrupt ( EPIM EPIS EPIF The CAN module has entered the error-passive state. This inter- rupt source is active if the status of the CAN module changes from the error-active mode to the error-passive mode. If the bit in (and ) is reset and the error-passive mode is still CAN_GIS...
Page 539 CAN Module • – Lost arbitration. Counter is incremented every UCCNF[3:0] = 0x8 time arbitration on the CAN line is lost during transmission. • – Transmission aborted. Counter is incre- UCCNF[3:0] = 0x9 mented every time arbitration is lost or a transmit request is cancelled ( is set).
Page 540: Can Warnings And Errors
Functional Operation CAN Warnings and Errors CAN warnings and errors are controlled using the register, the CAN_CEC register, and the register. CAN_ESR CAN_EWR Programmable Warning Limits It is possible to program the warning level for (error warning trans- EWTIS mit interrupt status) and (error warning receive interrupt status) EWRIS separately by writing to the error warning level error count fields for...
Page 541: Error Frames
CAN Module • Acknowledge error An acknowledge error occurs whenever a message has been sent and no receivers drive an acknowledge bit. • CRC error A CRC error occurs whenever a receiver calculates the CRC on the data it received and finds it different than the CRC that was trans- mitted on the bus itself.
Page 542 Functional Operation All receivers that did not detect the transmission error in the first instance now detect a stuff bit error. The transmitter may detect a normal bit error sooner. It aborts the transmission of the ongoing frame and tries sending it again later.
Page 543: Error Levels
CAN Module After having received 8 recessive bits, every node knows that the error con- dition has been resolved and starts transmission if messages are pending. The former transmitter that had to abort its operation must win the new arbitration again, otherwise its message is delayed as determined by priority.
Page 544 Functional Operation If either of the error counters exceeds 127, the CAN module goes into a passive state and the CAN error passive mode ( ) bit in is set. CAN_STATUS Then, it is not allowed to send any more active error frames. However, it is still allowed to transmit messages and to signal passive error frames in case the transmission fails because of a bit error.
Page 545: Debug And Test Modes
CAN Module Additionally, interrupts can occur for all of these levels by unmasking them in the global interrupt mask register ( ) shown on page 9-47. CAN_GIM The interrupts include the bus off interrupt ( ), the error-passive inter- BOIM rupt ( ), the error warning receive interrupt ( ), and the error...
Page 546 Functional Operation Listing 9-1. Enabling CAN Debug Features in C #include <cdefBF537.h> /* Enable debug mode, CDE must be set before other flags can be changed in register */ *pCAN_DEBUG |= CDE ; /* Set debug flags */ *pCAN_DEBUG &= ~DTO ; *pCAN_DEBUG |= MRB | MAA | DIL ;...
Page 547 CAN Module The mode auto acknowledge bit ( ) allows the CAN module to generate its own acknowledge during the ACK slot of the CAN frame. No external devices or connections are necessary to read back a transmit message. In this mode, the message that is sent is automatically stored in the internal receive buffer.
Page 548 Functional Operation Table 9-4. CAN Test Modes Functional Description Normal mode, not debug mode. No read back of transmit message. Normal transmission on CAN bus line. Read back. External acknowledge from external device required. Normal transmission on CAN bus line. Read back.
Page 549: Low Power Features
CAN Module Table 9-4. CAN Test Modes (Cont’d) Functional Description No transmission on CAN bus line. Read back. No external acknowledge required. Neither transmit message nor acknowledge are transmitted on CANTX. CANRX input is ignored. Internal loop is enabled. Low Power Features The Blackfin processor provides a low power hibernate state, and the CAN module includes built-in sleep and suspend modes to save power.
Page 550: Can Built-In Sleep Mode
Functional Operation The suspend mode can subsequently be exited by clearing the bit in . The only differences between suspend mode and configura- CAN_CONTROL tion mode are that writes to the registers are CAN_CLOCK CAN_TIMING still locked in suspend mode and the CAN control and status registers are not reset when exiting suspend mode.
Page 551: Register Definitions
CAN Module recessive logic ‘1’ level onto the pin. If the transceiver then senses CANRX CAN bus activity, it will, in turn, drive the pin to the dominant CANRX logic ‘0’ level. This signals to the Blackfin processor that CAN bus activity has been detected.
Page 552 Register Definitions Table 9-5. CAN Global Register Mapping (Cont’d) Register Name Function Notes CAN_TIMING CAN timing regis- Accessible only in configuration mode CAN_INTR CAN interrupt reg- Reserved bits 15:8 and 5:4 must always be ister written as ‘0’ CAN_GIM Global interrupt Bits 15:11 are reserved mask register CAN_GIS...
Page 553 CAN Module Table 9-7. CAN Mailbox Control Register Mapping Register Name Function Notes CAN_MCx Mailbox configura- Always disable before modifying mailbox area tion registers or direction CAN_MDx Mailbox direction Never change MDn direction when mailbox n registers is enabled. MD[31:24] and MD[7:0] are read only CAN_RMPx Receive message...
Page 554: Global Registers
Register Definitions Table 9-7. CAN Mailbox Control Register Mapping (Cont’d) Register Name Function Notes CAN_MBTIFx Mailbox transmit Can be cleared if mailbox or mailbox interrupt interrupt flag regis- is disabled. Changing direction while MBTIFn ters = 1 results in MBRIFn = 1 and MBTIFn = 0 CAN_MBRIFx Mailbox receive Can be cleared if mailbox or mailbox interrupt...
Page 555: Can_Control Register
CAN Module CAN_CONTROL Register Master Control Register (CAN_CONTROL) 15 14 13 12 11 10 0xFFC0 2AA0 Reset = 0x0080 SRS (Software Reset) CCR (CAN Configuration Mode Request) 0 - No effect 1 - Reset 0 - Cancelled DNM (DeviceNet Mode) 1 - Requested CSR (CAN Suspend Mode 0 - Disable...
Page 556: Can_Status Register
Register Definitions CAN_STATUS Register Global Status Register (CAN_STATUS) 15 14 13 12 11 10 0xFFC0 2A8C Reset = 0x0000 WT (CAN Transmit Warning REC (Receive Flag) Mode) 0 - TXECNT below limit 0 - Not in receive mode 1 - TXECNT at limit 1 - In receive mode WR (CAN Receive Warning TRM (Transmit...
Page 557: Can_Debug Register
CAN Module CAN_DEBUG Register CAN Debug Register (CAN_DEBUG) 15 14 13 12 11 10 0xFFC0 2A88 Reset = 0x0008 DEC (Disable Transmit and CDE (CAN Debug Receive Error Counters) Mode Enable) 0 - Enable CAN_CEC transmit 0 - Debug mode disabled and receive error counters 1 - Debug mode enabled 1 - Disable CAN_CEC transmit...
Page 558: Can_Timing Register
Register Definitions CAN_TIMING Register CAN Timing Register (CAN_TIMING) 15 14 13 12 11 10 0xFFC0 2A84 Reset = 0x0000 TSEG1[3:0] (Time Segment 1) SJW[1:0] (Synchronization Jump Width) TSEG2[2:0] (Time Segment 2) SAM (Sampling) Figure 9-15. CAN Timing Register CAN_INTR Register CAN Interrupt Register (CAN_INTR) 15 14 13 12 11 10 Reset = 0x00X0 ( X =...
Page 559: Can_Gim Register
CAN Module CAN_GIM Register Global Interrupt Mask Register (CAN_GIM) 15 14 13 12 11 10 0xFFC0 2A98 Reset = 0x0080 EWTIM (Error Warning Transmit ADIM (Access Denied Interrupt Mask) Interrupt Mask) EXTIM (External Trigger Interrupt Mask) EWRIM (Error Warning Receive UCEIM (Universal Counter Exceeded Interrupt Mask) Interrupt Mask)
Page 560: Can_Gif Register
Register Definitions CAN_GIF Register Global Interrupt Flag Register (CAN_GIF) 15 14 13 12 11 10 0xFFC0 2A9C Reset = 0x0000 EWTIF (Error Warning ADIF (Access Denied Interrupt Flag) Transmit Interrupt Flag) EXTIF (External Trigger Interrupt Flag) EWRIF (Error Warning UCEIF (Universal Counter Exceeded Receive Interrupt Flag) Interrupt Flag) EPIF (Error Passive Interrupt...
Page 561: Can_Amxx Registers
CAN Module CAN_AMxx Registers Acceptance Mask Register (CAN_AMxxH) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-10. EXTID[17:16] (Extended Identifier) BASEID[10:0] (Base Identifier) AMIDE (Acceptance Mask Identifier Extension) FMD (Full Mask Data) FDF (Filter on Data Field) Figure 9-20.
Page 562 Register Definitions Table 9-10. Acceptance Mask Register (H) Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_AM12H 0xFFC0 2B64 CAN_AM13H 0xFFC0 2B6C CAN_AM14H 0xFFC0 2B74 CAN_AM15H 0xFFC0 2B7C CAN_AM16H 0xFFC0 2B84 CAN_AM17H 0xFFC0 2B8C CAN_AM18H 0xFFC0 2B94 CAN_AM19H 0xFFC0 2B9C CAN_AM20H 0xFFC0 2BA4 CAN_AM21H 0xFFC0 2BAC...
Page 563 CAN Module Acceptance Mask Register (CAN_AMxxL) 15 14 13 12 11 10 For Memory- Reset = 0xXXXX mapped addresses, Table 9-11. EXTID[15:0]/DFM[15:0] (Extended Identifier/Data Field Mask) Figure 9-21. Acceptance Mask Register (L) Table 9-11. Acceptance Mask Register (L) Memory-mapped Addresses Register Name Memory-mapped Address CAN_AM00L...
Page 564 Register Definitions Table 9-11. Acceptance Mask Register (L) Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_AM16L 0xFFC0 2B80 CAN_AM17L 0xFFC0 2B88 CAN_AM18L 0xFFC0 2B90 CAN_AM19L 0xFFC0 2B98 CAN_AM20L 0xFFC0 2BA0 CAN_AM21L 0xFFC0 2BA8 CAN_AM22L 0xFFC0 2BB0 CAN_AM23L 0xFFC0 2BB8 CAN_AM24L 0xFFC0 2BC0 CAN_AM25L 0xFFC0 2BC8...
Page 565: Can_Mbxx_Id1 Registers
CAN Module CAN_MBxx_ID1 Registers Mailbox Word 7 Register (CAN_MBxx_ID1) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-12. EXTID[17:16] (Extended Identifier) BASEID[10:0] (Base Identifier) IDE (Identifier Extension) RTR (Remote Transmission Request) AME (Acceptance Mask Enable) Figure 9-22.
Page 566 Register Definitions Table 9-12. Mailbox Word 7 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB13_ID1 0xFFC0 2DBC CAN_MB14_ID1 0xFFC0 2DDC CAN_MB15_ID1 0xFFC0 2DFC CAN_MB16_ID1 0xFFC0 2E1C CAN_MB17_ID1 0xFFC0 2E3C CAN_MB18_ID1 0xFFC0 2E5C CAN_MB19_ID1 0xFFC0 2E7C CAN_MB20_ID1 0xFFC0 2E9C CAN_MB21_ID1 0xFFC0 2EBC CAN_MB22_ID1 0xFFC0 2EDC...
Page 567: Can_Mbxx_Id0 Registers
CAN Module CAN_MBxx_ID0 Registers Mailbox Word 6 Register (CAN_MBxx_ID0) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-13. EXTID[15:0]/DFC[15:0] (Extended Identifier/Data Field Acceptance Code) Figure 9-23. Mailbox Word 6 Register Table 9-13. Mailbox Word 6 Register Memory-mapped Addresses Register Name Memory-mapped Address...
Page 568 Register Definitions Table 9-13. Mailbox Word 6 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB15_ID0 0xFFC0 2DF8 CAN_MB16_ID0 0xFFC0 2E18 CAN_MB17_ID0 0xFFC0 2E38 CAN_MB18_ID0 0xFFC0 2E58 CAN_MB19_ID0 0xFFC0 2E78 CAN_MB20_ID0 0xFFC0 2E98 CAN_MB21_ID0 0xFFC0 2EB8 CAN_MB22_ID0 0xFFC0 2ED8 CAN_MB23_ID0 0xFFC0 2EF8 CAN_MB24_ID0 0xFFC0 2F18...
Page 569: Can_Mbxx_Timestamp Registers
CAN Module CAN_MBxx_TIMESTAMP Registers Mailbox Word 5 Register (CAN_MBxx_TIMESTAMP) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-14. TSV[15:0] (Time Stamp Value) Figure 9-24. Mailbox Word 5 Register Table 9-14. Mailbox Word 5 Register Memory-mapped Addresses Register Name Memory-mapped Address...
Page 570 Register Definitions Table 9-14. Mailbox Word 5 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB15_TIMESTAMP 0xFFC0 2DF4 CAN_MB16_TIMESTAMP 0xFFC0 2E14 CAN_MB17_TIMESTAMP 0xFFC0 2E34 CAN_MB18_TIMESTAMP 0xFFC0 2E54 CAN_MB19_TIMESTAMP 0xFFC0 2E74 CAN_MB20_TIMESTAMP 0xFFC0 2E94 CAN_MB21_TIMESTAMP 0xFFC0 2EB4 CAN_MB22_TIMESTAMP 0xFFC0 2ED4 CAN_MB23_TIMESTAMP 0xFFC0 2EF4 CAN_MB24_TIMESTAMP 0xFFC0 2F14...
Page 571: Can_Mbxx_Length Registers
CAN Module CAN_MBxx_LENGTH Registers Mailbox Word 4 Register (CAN_MBxx_LENGTH) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-25. DLC[3:0] (Data Length Code) Figure 9-25. Mailbox Word 4 Register Table 9-15. Mailbox Word 4 Register Memory-mapped Addresses Register Name Memory-mapped Address...
Page 572 Register Definitions Table 9-15. Mailbox Word 4 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB15_LENGTH 0xFFC0 2DF0 CAN_MB16_LENGTH 0xFFC0 2E10 CAN_MB17_LENGTH 0xFFC0 2E30 CAN_MB18_LENGTH 0xFFC0 2E50 CAN_MB19_LENGTH 0xFFC0 2E70 CAN_MB20_LENGTH 0xFFC0 2E90 CAN_MB21_LENGTH 0xFFC0 2EB0 CAN_MB22_LENGTH 0xFFC0 2ED0 CAN_MB23_LENGTH 0xFFC0 2EF0 CAN_MB24_LENGTH 0xFFC0 2F10...
Page 573: Can_Mbxx_Datax Registers
CAN Module CAN_MBxx_DATAx Registers Mailbox Word 3 Register (CAN_MBxx_DATA3) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-16. Data Field Byte 0[7:0] Data Field Byte 1[7:0] Figure 9-26. Mailbox Word 3 Register Table 9-16. Mailbox Word 3 Register Memory-mapped Addresses Register Name Memory-mapped Address...
Page 574 Register Definitions Table 9-16. Mailbox Word 3 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB14_DATA3 0xFFC0 2DCC CAN_MB15_DATA3 0xFFC0 2DEC CAN_MB16_DATA3 0xFFC0 2E0C CAN_MB17_DATA3 0xFFC0 2E2C CAN_MB18_DATA3 0xFFC0 2E4C CAN_MB19_DATA3 0xFFC0 2E6C CAN_MB20_DATA3 0xFFC0 2E8C CAN_MB21_DATA3 0xFFC0 2EAC CAN_MB22_DATA3 0xFFC0 2ECC CAN_MB23_DATA3 0xFFC0 2EEC...
Page 575 CAN Module Mailbox Word 2 Register (CAN_MBxx_DATA2) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-17. Data Field Byte 2[7:0] Data Field Byte 3[7:0] Figure 9-27. Mailbox Word 2 Register Table 9-17. Mailbox Word 2 Register Memory-mapped Addresses Register Name Memory-mapped Address...
Page 576 Register Definitions Table 9-17. Mailbox Word 2 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB16_DATA2 0xFFC0 2E08 CAN_MB17_DATA2 0xFFC0 2E28 CAN_MB18_DATA2 0xFFC0 2E48 CAN_MB19_DATA2 0xFFC0 2E68 CAN_MB20_DATA2 0xFFC0 2E88 CAN_MB21_DATA2 0xFFC0 2EA8 CAN_MB22_DATA2 0xFFC0 2EC8 CAN_MB23_DATA2 0xFFC0 2EE8 CAN_MB24_DATA2 0xFFC0 2F08 CAN_MB25_DATA2 0xFFC0 2F28...
Page 577 CAN Module Mailbox Word 1 Register (CAN_MBxx_DATA1) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-18. Data Field Byte 4[7:0] Data Field Byte 5[7:0] Figure 9-28. Mailbox Word 1 Register Table 9-18. Mailbox Word 1 Register Memory-mapped Addresses Register Name Memory-mapped Address...
Page 578 Register Definitions Table 9-18. Mailbox Word 1 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB16_DATA1 0xFFC0 2E04 CAN_MB17_DATA1 0xFFC0 2E24 CAN_MB18_DATA1 0xFFC0 2E44 CAN_MB19_DATA1 0xFFC0 2E64 CAN_MB20_DATA1 0xFFC0 2E84 CAN_MB21_DATA1 0xFFC0 2EA4 CAN_MB22_DATA1 0xFFC0 2EC4 CAN_MB23_DATA1 0xFFC0 2EE4 CAN_MB24_DATA1 0xFFC0 2F04 CAN_MB25_DATA1 0xFFC0 2F24...
Page 579 CAN Module Mailbox Word 0 Register (CAN_MBxx_DATA0) 15 14 13 12 11 10 Reset = 0xXXXX For Memory- mapped addresses, Table 9-19. Data Field Byte 6[7:0] Data Field Byte 7[7:0] Figure 9-29. Mailbox Word 0 Register Table 9-19. Mailbox Word 0 Register Memory-mapped Addresses Register Name Memory-mapped Address...
Page 580: Mailbox Control Registers
Register Definitions Table 9-19. Mailbox Word 0 Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address CAN_MB16_DATA0 0xFFC0 2E00 CAN_MB17_DATA0 0xFFC0 2E20 CAN_MB18_DATA0 0xFFC0 2E40 CAN_MB19_DATA0 0xFFC0 2E60 CAN_MB20_DATA0 0xFFC0 2E80 CAN_MB21_DATA0 0xFFC0 2EA0 CAN_MB22_DATA0 0xFFC0 2EC0 CAN_MB23_DATA0 0xFFC0 2EE0 CAN_MB24_DATA0 0xFFC0 2F00 CAN_MB25_DATA0 0xFFC0 2F20...
Page 581: Can_Mcx Registers
CAN Module CAN_MCx Registers Mailbox Configuration Register 1 (CAN_MC1) For all bits, 0 - Mailbox disabled, 1 - Mailbox enabled 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A00 MC15 MC14 MC13 MC12 MC11 MC10 Figure 9-30. Mailbox Configuration Register 1 Mailbox Configuration Register 2 (CAN_MC2) For all bits, 0 - Mailbox disabled, 1 - Mailbox enabled 15 14 13 12 11 10...
Page 582: Can_Mdx Registers
Register Definitions CAN_MDx Registers Mailbox Direction Register 1 (CAN_MD1) For all bits, 0 - Mailbox configured as transmit mode, 1 - Mailbox configured as receive mode 15 14 13 12 11 10 Reset = 0x00FF 0xFFC0 2A04 MD15 MD0 - RO MD14 MD1 - RO MD13...
Page 583: Can_Rmpx Register
CAN Module CAN_RMPx Register Receive Message Pending Register 1 (CAN_RMP1) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A18 RMP15 RMP0 RMP14 RMP1 RMP13 RMP2 RMP12 RMP3 RMP11 RMP4 RMP10 RMP5 RMP9 RMP6 RMP8 RMP7 Figure 9-34.
Page 584: Can_Rmlx Register
Register Definitions CAN_RMLx Register Receive Message Lost Register 1 (CAN_RML1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A1C RML15 RML0 RML14 RML1 RML13 RML2 RML12 RML3 RML11 RML4 RML10 RML5 RML9 RML6 RML8 RML7 Figure 9-36. Receive Message Lost Register 1 Receive Message Lost Register 2 (CAN_RML2) 15 14 13 12 11 10 Reset = 0x0000...
Page 585: Can_Opssx Register
CAN Module CAN_OPSSx Register Overwrite Protection/Single Shot Transmission Register 1 (CAN_OPSS1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A30 OPSS15 OPSS0 OPSS14 OPSS1 OPSS13 OPSS2 OPSS12 OPSS3 OPSS11 OPSS4 OPSS10 OPSS5 OPSS9 OPSS6 OPSS8 OPSS7 Figure 9-38. Overwrite Protection/Single Shot Transmission Register 1 Overwrite Protection/Single Shot Transmission Register 2 (CAN_OPSS2) 15 14 13 12 11 10 Reset = 0x0000...
Page 586: Can_Trsx Registers
Register Definitions CAN_TRSx Registers Transmission Request Set Register 1 (CAN_TRS1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A08 TRS15 TRS0 - RO TRS14 TRS1 - RO TRS13 TRS2 - RO TRS12 TRS3 - RO TRS11 TRS4 - RO TRS10 TRS5 - RO TRS9...
Page 587: Can_Trrx Registers
CAN Module CAN_TRRx Registers Transmission Request Reset Register 1 (CAN_TRR1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A0C TRR15 TRR0 - RO TRR14 TRR1 - RO TRR13 TRR2 - RO TRR12 TRR3 - RO TRR11 TRR4 - RO TRR10 TRR5 - RO TRR9...
Page 588: Can_Aax Register
Register Definitions CAN_AAx Register Abort Acknowledge Register 1 (CAN_AA1) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A14 AA15 AA0 - RO AA14 AA1 - RO AA13 AA2 - RO AA12 AA3 - RO AA11 AA4 - RO AA10...
Page 589: Can_Tax Register
CAN Module CAN_TAx Register Transmission Acknowledge Register 1 (CAN_TA1) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A10 TA15 TA0 - RO TA14 TA1 - RO TA13 TA2 - RO TA12 TA3 - RO TA11 TA4 - RO TA10...
Page 590: Can_Mbtd Register
Register Definitions CAN_MBTD Register Temporary Mailbox Disable Feature Register (CAN_MBTD) 15 14 13 12 11 10 0xFFC0 2AAC Reset = 0x0000 TDPTR[4:0] (Temporary Disable Pointer) TDA (Temporary Disable Acknowledge) TDR (Temporary Disable Request) Figure 9-48. Temporary Mailbox Disable Register CAN_RFHx Registers Remote Frame Handling Register 1 (CAN_RFH1) 15 14 13 12 11 10 Reset = 0x0000...
Page 591: Can_Mbimx Registers
CAN Module Remote Frame Handling Register 2 (CAN_RFH2) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A6C RFH31 - RO RFH16 RFH30 - RO RFH17 RFH29 - RO RFH18 RFH28 - RO RFH19 RFH27 - RO RFH20 RFH26 - RO RFH21 RFH25 - RO RFH22...
Page 592: Can_Mbtifx Registers
Register Definitions Mailbox Interrupt Mask Register 2 (CAN_MBIM2) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A68 MBIM31 MBIM16 MBIM30 MBIM17 MBIM29 MBIM18 MBIM28 MBIM19 MBIM27 MBIM20 MBIM26 MBIM21 MBIM25 MBIM22 MBIM24 MBIM23 Figure 9-52. Mailbox Interrupt Mask Register 2 CAN_MBTIFx Registers Mailbox Transmit Interrupt Flag Register 1 (CAN_MBTIF1) All bits are W1C...
Page 593: Can_Mbrifx Registers
CAN Module Mailbox Transmit Interrupt Flag Register 2 (CAN_MBTIF2) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A60 MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF MBTIF Figure 9-54.
Page 594: Universal Counter Registers
Register Definitions Mailbox Receive Interrupt Flag Register 2 (CAN_MBRIF2) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A64 MBRIF MBRIF 31 - RO MBRIF MBRIF 30 - RO MBRIF MBRIF 29 - RO MBRIF MBRIF 28 - RO MBRIF...
Page 595: Can_Uccnf Register
CAN Module CAN_UCCNF Register Universal Counter Configuration Mode Register (CAN_UCCNF) 15 14 13 12 11 10 0xFFC0 2ACC Reset = 0x0000 UCCNF[3:0] (Universal UCE (Universal Counter Counter Configuration) Enable) 0x0 - Reserved 0 - Counter disabled 0x1 - Time stamp mode 1 - Counter enabled 0x2 - Watchdog mode UCCT (Universal Counter...
Page 596: Can_Uccnt Register
Register Definitions CAN_UCCNT Register Universal Counter Register (CAN_UCCNT) 15 14 13 12 11 10 0xFFC0 2AC4 Reset = 0x0000 UCCNT[15:0] Figure 9-58. Universal Counter Register CAN_UCRC Register Universal Counter Reload/Capture Register (CAN_UCRC) 15 14 13 12 11 10 0xFFC0 2AC8 Reset = 0x0000 UCRC[15:0] Figure 9-59.
Page 597: Error Registers
CAN Module Error Registers Figure 9-60 through Figure 9-62 show the CAN error registers. CAN_CEC Register CAN Error Counter Register (CAN_CEC) 15 14 13 12 11 10 0xFFC0 2A90 Reset = 0x0000 TXECNT[7:0] (Transmit Error RXECNT[7:0] (Receive Error Counter) Counter) Figure 9-60.
Page 598: Can_Ewr Register
Register Definitions CAN_EWR Register CAN Error Counter Warning Level Register (CAN_EWR) 15 14 13 12 11 10 Reset = 0x6060 0xFFC0 2AB0 EWLTEC[7:0] (Transmit Error EWLREC[7:0] (Receive Error Warning Limit) Warning Limit) Figure 9-62. CAN Error Counter Warning Level Register 9-86 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 599: Programming Examples
CAN Module Programming Examples The following CAN code examples (Listing 9-2 through Listing 9-4 on page 9-91) show how to program the CAN hardware and timing, initialize mailboxes, perform transfers, and service interrupts. Each of these code examples assumes that the appropriate header file is included in the source code (that is, for ADSP-BF537 projects).
Page 600 Programming Examples R0 = 0x0334(Z); /* SJW = 3, TSEG2 = 3, TSEG1 = 4 */ W[P0] = R0; SSYNC; /* =================================================== ** CAN_CLOCK - Calculate Prescaler (BRP) ** Assume a 500kbps CAN rate is desired, which means ** the duration of the bit on the CAN bus (tBIT) is ** 2us.
Page 601: Initializing And Enabling Can Mailboxes
CAN Module Initializing and Enabling CAN Mailboxes Before the CAN can transfer data, the mailbox area must be properly set up and the controller must be initialized properly. Listing 9-3. Initializing and Enabling Mailboxes CAN_Initialize_Mailboxes: P0.H = HI(CAN_MD1); /* Configure Mailbox Direction */ P0.L = LO(CAN_MD1);...
Page 602: Initiating Can Transfers And Processing Interrupts
Programming Examples W[P0] = R0; /* Set DLC to 4 Bytes */ R0 = 0xAABB(Z); P0.L = LO(CAN_MB_DATA3(8)); W[P0] = R0; /* Byte0 = 0xAA, Byte1 = 0xBB */ R0 = 1; P0.L = LO(CAN_MB_DATA2(8)); W[P0] = R0; /* Initialize Count to 1 */ /* Initialize Mailbox 9 For Receive */ R0 = 0x007 <<...
Page 603 CAN Module and then waits for and processes CAN TX and RX interrupts. This example assumes that the have been CAN_RX_HANDLER CAN_TX_HANDLER properly registered in the system interrupt controller and that the inter- rupts are enabled properly in the register. SIC_IMASK Listing 9-4.
Page 604 Programming Examples JUMP Wait_Here_For_IRQs; /* =================================================== ** CAN_TX_HANDLER ** ISR clears the interrupt request from MB8, writes ** new data to be sent, and requests to send again ** =================================================== CAN_TX_HANDLER: [--SP] = (R7:6, P5:5); /* Save Clobbered Registers */ [--SP] = ASTAT;...
Page 605 CAN Module W[P5] = R7; /* Issue New Transmit Request */ ASTAT = [SP++]; /* Restore Clobbered Registers */ (R7:6, P5:5) = [SP++]; SSYNC; RTI; /* =================================================== ** CAN_RX_HANDLER ** ISR clears the interrupt request from MB9, writes ** new data to be sent, and requests to send again ** =================================================== CAN_RX_HANDLER: [--SP] = (R7:7, P5:4);...
Page 606 Programming Examples 9-94 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 607: Overview
10 SPI COMPATIBLE PORT CONTROLLERS This chapter describes the Serial Peripheral Interface (SPI) port. Follow- ing an overview and a list of key features is a description of operation and functional modes of operation. The chapter concludes with a program- ming model, consolidated register definitions, and programming examples.
Page 608 Features • Programmable baud rate, clock phase, and polarity • Supports multimaster environments • Integrated DMA controller • Double-buffered transmitter and receiver • 7 SPI chip select outputs, 1 SPI device select input • Programmable shift direction of MSB or LSB first •...
Page 609: Interface Overview
SPI Compatible Port Controllers Interface Overview Figure 10-1 provides a block diagram of the SPI. The interface is essen- tially a shift register that serially transmits and receives data bits, one bit at a time at the rate, to and from other SPI devices. SPI data is transmit- ted and received at the same time through the use of a shift register.
Page 610: External Interface
Interface Overview External Interface Most of the SPI signals are accessible through Port F. The five most important signals ( , and ) are not multi- MISO MOSI SPISS SPISSEL1 plexed with other peripherals. However, by default they function as GPIOs and are individually enabled by the respective bits in the register.
Page 611: Master Out Slave In (Mosi)
SPI Compatible Port Controllers signal can connect to the pin which functions as a GPIO by PF13 default. To enable this pin for use as the SPI clock signal, be sure to first configure the register to enable the pin for peripheral use PORTF_FER PF13 (see...
Page 612: Serial Peripheral Interface Slave Select Input Signal
Interface Overview The SPI signal can connect to the pin which functions as a MISO PF12 GPIO by default. To enable this pin for use as the SPI signal, be sure MISO to first configure the register to enable the pin for periph- PORTF_FER PF12...
Page 613: Enable Output Signals
SPI Compatible Port Controllers signal can connect to the pin which functions as a GPIO SPISS PF14 by default. To enable this pin for use as the SPI slave-select input signal, be sure to first configure the register to enable the pin for PORTF_FER PF14...
Page 614 Interface Overview These signals are always active low in the SPI protocol. Since the respec- tive pins are not driven during reset, it is recommended to pull them up by a resistor. Table 10-1 summarizes how to setup the port control logic in order to enable the individual slave select enable outputs.
Page 615 SPI Compatible Port Controllers In slave mode, the bits have no effect, and each SPI uses the SPI_FLG input as a slave select. Just as in the master mode case, the SPISS PF14 must first be configured as a peripheral pin in the register, and PORT_MUX then as an SPI pin in the...
Page 616: Slave Select Inputs
Interface Overview Slave Select Inputs If the SPI is in slave mode, acts as the slave select input. When SPISS enabled as a master, can serve as an error detection input for the SPI SPISS in a multimaster environment. The bit in enables this fea- PSSE...
Page 617 SPI Compatible Port Controllers some other microcontrollers. Therefore, it is possible to use the feature with any other SPI device that includes this EMISO functionality. Figure 10-4 shows one processor as a master with three processors (or other SPI compatible devices) as slaves. SLAVE DEVICE SLAVE DEVICE SLAVE DEVICE...
Page 618: Internal Interfaces
Interface Overview When using DMA for SPI transmit, the interrupt signi- DMA_DONE fies that the DMA FIFO is empty. However, at this point there may still be data in the SPI DMA FIFO waiting to be transmitted. Therefore, software needs to poll in the register until SPI_STAT...
Page 619: Spi Transmit Data Buffer
SPI Compatible Port Controllers When configured as a receive channel, what is transmitted is irrelevant. A 16-bit by four-word FIFO (without burst capability) is included to improve throughput on the DAB. When using DMA for SPI transmit, the interrupt signi- DMA_DONE fies that the DMA FIFO is empty.
Page 620: Spi Receive Data Buffer
Description of Operation If multiple writes to occur while a transfer is already in progress, SPI_TDBR only the last data written is transmitted. None of the intermediate values written to are transmitted. Multiple writes to are pos- SPI_TDBR SPI_TDBR sible, but not recommended. SPI Receive Data Buffer register is a 16-bit read-only register.
Page 621 SPI Compatible Port Controllers shown for —one for and the other for . The dia- CPOL = 0 CPOL = 1 grams may be interpreted as master or slave timing diagrams since the , and pins are directly connected between the master and the MISO MOSI slave.
Page 622 Description of Operation (CPOL = 0) (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SPISS (TO SLAVE) (* = UNDEFINED) Figure 10-5. SPI Transfer Protocol for CPHA = 0 (CPOL = 0) (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SPISS (TO SLAVE)
Page 623: Spi General Operation
SPI Compatible Port Controllers SPI General Operation The SPI can be used in a single master as well as multimaster environ- ment. The , and the signals are all tied together in both MOSI MISO configurations. SPI transmission and reception are always enabled simul- taneously, unless the broadcast mode has been selected.
Page 624: Spi Control
Description of Operation the slave and accepts new data from the master into its shift register, while it transmits requested data out of the shift register through its SPI trans- mit data pin. Multiple processors can take turns being the master device, as can other microcontrollers or microprocessors.
Page 625: Clock Signals
SPI Compatible Port Controllers transaction is initiated by enabling the SPI for DMA receive mode. Subse- quent individual transactions are initiated by a DMA read of the . A value of 11 selects DMA transmit mode and the transaction is SPI_RDBR initiated by a DMA write of the SPI_TDBR...
Page 626: Spi Baud Rate
Description of Operation SPI Baud Rate register is used to set the bit transfer rate for a master SPI_BAUD device. When configured as a slave, the value written to this register is ignored. The serial clock frequency is determined by this formula: SCK Frequency = (Peripheral clock frequency SCLK)/(2 x SPI_BAUD) Writing a value of 0 or 1 to the register disables the serial clock.
Page 627: Mode Fault Error (Modf)
SPI Compatible Port Controllers software. To clear a sticky bit, the user must write a 1 to the desired bit position of . For example, if the bit is set, the user must write SPI_STAT a 1 to bit 2 of to clear the error condition.
Page 628: Transmission Error (Txe)
Description of Operation When are cleared, the SPI data and clock pin drivers ( MSTR MOSI , and ) are disabled. However, the slave select output pins revert to MISO being controlled by the general-purpose I/O port registers. This could lead to contention on the slave select lines if these lines are still driven by the processor.
Page 629: Interrupt Output
SPI Compatible Port Controllers into the shift register and transmitted. In this case, the data in SPI_TDBR may not match what was transmitted. This error can easily be avoided by proper software control. The bit is sticky (W1C). TXCOL Interrupt Output The SPI has two interrupt output signals: a data interrupt and an error interrupt.
Page 630: Master Mode Operation
Functional Description Master Mode Operation When the SPI is configured as a master (and DMA mode is not selected), the interface operates in the following manner. 1. The core writes to the and/or registers to PORTF_FER PORT_MUX properly configure the required and/or pins for SPI use as slave-select outputs and, if necessary, multimaster detection input...
Page 631: Transfer Initiation From Master (Transfer Modes)
SPI Compatible Port Controllers If the transmit buffer remains empty or the receive buffer remains full, the device operates according to the states of the bits in . If SPI_CTL and the transmit buffer is empty, the device repeatedly transmits 0s SZ = 1 on the pin.
Page 632: Slave Mode Operation
Functional Description Table 10-4. Transfer Initiation (Cont’d) TIMOD Function Transfer Initiated Upon Action, Interrupt Receive with Initiate new multiword trans- Request DMA reads as long as fer upon enabling SPI for SPI DMA FIFO is not empty. DMA mode. Individual word transfers begin with a DMA read of SPI_RDBR, and last transfer completed.
Page 633: Slave Ready For A Transfer
SPI Compatible Port Controllers 5. Reception/transmission continues until is released or until SPISS the slave has received the proper number of clock cycles. 6. The slave device continues to receive/transmit with each new fall- ing edge transition on and/or active clock edge.
Page 634: Programming Model
Programming Model Programming Model The following sections describe the SPI programming model. Beginning and Ending an SPI Transfer The start and finish of an SPI transfer depend on whether the device is configured as a master or a slave, whether the mode is selected, and CPHA whether the transfer initiation mode (...
Page 635 SPI Compatible Port Controllers is cleared shortly after the start of a transfer ( going low for SPISS , first active edge of ), and is set at the same time CPHA = 0 CPHA = 1 For a master device, is cleared shortly after the start of a RXS.
Page 636: Master Mode Dma Operation
Programming Model only when operating in mode. With TIMOD TIMOD TIMOD , the interrupt is requested while the transfer is still in TIMOD progress. Master Mode DMA Operation When enabled as a master with the DMA engine configured to transmit or receive data, the SPI interface operates as follows.
Page 637 SPI Compatible Port Controllers If configured for transmit, the SPI requests a DMA read from memory. Upon a DMA grant, the DMA engine reads a word from memory and writes to the SPI DMA FIFO. As the SPI writes data from the SPI DMA FIFO into the register, it initiates a SPI_TDBR...
Page 638: Slave Mode Dma Operation
Programming Model is set). If , the device repeatedly transmits 0s on the pin. If SZ = 1 MOSI , it repeatedly transmits the contents of the register. The SZ = 0 SPI_TDBR underrun condition cannot generate an error interrupt in this mode. For transmit DMA operations, the master SPI initiates a word transfer only when there is data in the DMA FIFO.
Page 639 SPI Compatible Port Controllers The following steps illustrate the SPI receive or transmit DMA sequence in an SPI slave (in response to a master command). 1. The core writes to the register to properly configure the PORTF_FER pin as the input signal.
Page 640 Programming Model 5. In receive mode, as long as there is data in the SPI DMA FIFO (FIFO not empty), the SPI slave continues to request a DMA write to memory. The DMA engine continues to read a word from the SPI DMA FIFO and writes to memory until the SPI DMA word count register transitions from 1 to 0.
Page 641 SPI Compatible Port Controllers when configured in transmit DMA mode, including the data in the register, and the status of the bits. The over- SPI_RDBR RBSY RBSY run conditions cannot generate an error interrupt in this mode. Writes to the register during an active SPI transmit DMA opera- SPI_TDBR tion should not occur because the DMA data will be overwritten.
Page 642 Programming Model WRITE PORTF_FER TO ENABLE SPI SIGNALS WRITE PORT_MUX MASTER TO ENABLE PORT J MULTISLAVE MASTER OR SLAVE? SLAVES AND/OR SUPPORT? MORE PORT F SLAVES SLAVE, MSTR = 0 WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE MSTR = 1 WRITE SPI_CTL TO CONFIGURE SPI HARDWARE AND ENABLE SPI PORT WRITE SPI_FLG...
Page 643 SPI Compatible Port Controllers WRITE PORTF_FER TO ENABLE SPI SIGNALS WRITE DESIRED DMA CHANNEL'S DEFAULT DMA7 DMAx_PERIPHERAL_MAP WITH 0x7000 TO SET AS SPI. FOR SPI? (REPLACE ALL MENTION OF DMA7 REGISTER NAMES IN THIS FLOW CHART WITH CHOSEN DMAx PREFIX.) WRITE DMA7_CONFIG TO CONFIGURE DMA ENGINE 0x4 ARRAY 0x6 SMALL LIST...
Page 644 Programming Model WRITE DMA REGISTERS: 2D DMA? DMA7_Y_COUNT DMA7_Y_MODIFY SLAVE, MSTR = 0 IS SPI MASTER OR SLAVE? MASTER WRITE PORT_MUX TO ENABLE PORT J MULTI-SLAVE SLAVES AND/OR SUPPORT? MORE PORT F SLAVES WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE MSTR = 1 WRITE SPI_CTL TO CONFIGURE SPI PORT...
Page 645 SPI Compatible Port Controllers CLEAR INTERRUPT BY INTERRUPT WRITING THE DMA_DONE REQUESTED? BIT IN DMA7_IRQ_STATUS TERMINATE DMA? FLOW = STOP WRITE DMA7_CONFIG TO ENABLE DMA AGAIN TX OR RX DMA? WAIT FOR DMA_RUN = 0 IN DMA7_IRQ_STATUS WAIT FOR TWO STRAIGHT READS OF TXS = 0 IN SPI_STAT WAIT FOR SPIF = 1 IN SPI_STAT WRITE SPI_FLG TO...
Page 646: Spi Registers
SPI Registers SPI Registers The SPI peripheral includes a number of user-accessible registers. Some of these registers are also accessible through the DMA bus. Four registers contain control and status information: , and SPI_BAUD SPI_CTL SPI_FLG . Two registers are used for buffering receive and transmit data: SPI_STAT .
Page 647 SPI Compatible Port Controllers SPI Baud Rate Register (SPI_BAUD) 15 14 13 12 11 10 0xFFC0 0514 Reset = 0x0000 Baud Rate[15:0] SCLK / (2 × SPI_BAUD) Figure 10-11. SPI Baud Rate Register SPI Control Register (SPI_CTL) 15 14 13 12 11 10 0xFFC0 0500 Reset = 0x0400 SPE (SPI Enable)
Page 648 SPI Registers SPI Flag Register (SPI_FLG) 15 14 13 12 11 10 0xFFC0 0504 Reset = 0xFF00 FLG7 (Slave FLS1 (Slave Select Enable 1) Select Value 7) 0 - SPISSEL1 disabled SPISSEL7 value 1 - SPISSEL1 enabled FLG6 (Slave Select FLS2 (Slave Select Enable 2) Value 6) 0 - SPISSEL2 disabled...
Page 649 SPI Compatible Port Controllers • Slave select value ( ) bits FLGx When a pin is configured as a slave select output, the bits FLGx can determine the value driven onto the output. If the bit in CPHA is set, the output value is set by software control of the SPI_CTL bits.
Page 650 SPI Registers SPI Transmit Data Buffer Register (SPI_TDBR) 15 14 13 12 11 10 0xFFC0 050C Reset = 0x0000 Transmit Data Buffer[15:0] Figure 10-15. SPI Transmit Data Buffer Register SPI Receive Data Buffer Register (SPI_RDBR) 15 14 13 12 11 10 0xFFC0 0510 Reset = 0x0000 Receive Data Buffer[15:0]...
Page 651: Programming Examples
SPI Compatible Port Controllers Programming Examples This section includes examples (Listing 10-1 through Listing 10-8 on page 10-52) for core generated transfer and for use with DMA. Each code example assumes that the appropriate header file is included. defBF53x Core Generated Transfer The following core-driven master-mode SPI example shows how to initial- ize the hardware, signal the start of a transfer, handle the interrupt and issue the next transfer, and generate a stop condition.
Page 652: Starting A Transfer
Programming Examples * TIMOD [1:0] = 00 : Transfer On RDBR Read. * SZ [2] 0 : Send Last Word When TDBR0 Is Empty * GM [3] 1 : Discard Incoming Data If RDBR0 Is Full * PSSE [4] 0 : Disables Slave-Select As Input (Master) * EMISO [5] 0 : MISO Disabled For Output (Master) * [7] and [6] =...
Page 653: Post Transfer And Next Transfer
SPI Compatible Port Controllers Listing 10-2. Initiate Transfer Initiate_Transfer: P0.H = hi(SPI_FLG); P0.L = lo(SPI_FLG); R0 = W[P0] (Z); BITCLR (R0,0xF); /* FLG7 */ W[P0] = R0; /* Drive 0 on enabled slave-select pin */ P0.H = hi(SPI_TDBR); /* SPI Transmit Register */ P0.L = lo(SPI_TDBR);...
Page 654: Stopping
Programming Examples R0 = W[P1++](z); /* Get next data to be transmitted */ W[P0] = R0.l; /* Write that data to SPI_TDBR */ Kick_Off_Next: P0.H = hi(SPI_RDBR); /* SPI receive register */ P0.L = lo(SPI_RDBR); R0 = W[P0] (z); /* Read SPI receive register (also kicks off next transfer) */ W[P2++] = R0;...
Page 655: Dma Initialization Sequence
SPI Compatible Port Controllers DMA Initialization Sequence The following code initializes the DMA to perform a 16-bit memory read DMA operation in autobuffer mode, and generates an interrupt request when the buffer has been sent. This code assumes that points to the start of the data buffer to be transmitted and that is a defined NUM_SAMPLES...
Page 656: Spi Initialization Sequence
Programming Examples SPI Initialization Sequence Before the SPI can transfer data, the registers must be configured as follows. Listing 10-6. SPI Initialization SPI_Register_Initialization: P0.H = hi(SPI_FLG); P0.L = lo(SPI_FLG); R0 = W[P0] (Z); BITSET (R0,0x7); /* FLS7 */ W[P0] = R0; /* Enable slave-select output pin */ P1.H = hi(SPI_BAUD);...
Page 657: Starting A Transfer
SPI Compatible Port Controllers * SPE [14] 1 : SPI module is enabled * [15] 0 : RESERVED ***************************************************/ /* Configure SPI as MASTER */ R1 = 0x190B(z); /* Leave disabled until DMA is enabled*/ P1.L = lo(SPI_CTL); W[P1] = R1; ssync; Starting a Transfer After the initialization procedure in the given master mode, a transfer begins following enabling of SPI.
Page 658 Programming Examples completed, is polled to determine when the transmit buffer is SPI_STAT empty. If there is data in the SPI Transmit FIFO, it is loaded as soon as bit clears. A second consecutive read with the bit clear indi- cates the FIFO is empty and the last word is in the shift register.
Page 659 SPI Compatible Port Controllers R2 = R2 & R1; CC = R0 == 0; IF !CC JUMP Check_TXS; R2 = W[P0] (Z); /* Check if TXS stays clear for 2 reads */ R2 = R2 & R1; CC = R0 == 0; IF !CC JUMP Check_TXS;...
Page 660 Programming Examples 10-54 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 661: Overview
11 TWO WIRE INTERFACE CONTROLLER This chapter describes the Two Wire Interface (TWI) port. Following an overview and a list of key features is a description of operation and func- tional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples.
Page 662: Interface Overview
Interface Overview • 100 kbits/second and 400 kbits/second data rates • General call address support • Master clock synchronization and support for clock low extension • Separate multiple-byte receive and transmit FIFOs • Low interrupt rate • Individual override control of data and clock lines in the event of bus lock-up •...
Page 663: External Interface
Two Wire Interface Controller TWI INTERFACE LOGIC CLOCK ADDRESS PRESCALER ARBITRATION GENERATION COMPARE Tx SHIFT REG Rx SHIFT REG 2-DEEP FIFO 2-DEEP FIFO Tx REG Rx REG Figure 11-1. TWI Block Diagram External Interface The TWI signals are dedicated to this interface, that is, they are not multi- plexed with any other signals.
Page 664: Serial Data Signal (Sda)
Interface Overview In master mode the TWI controller must set this signal to the desired fre- quency. The TWI controller supports the standard mode of operation (up to 100 KHz) or fast mode (up to 400 KHz). The TWI control register ( ) is used to set the value TWI_CONTROL...
Page 665: Internal Interfaces
Two Wire Interface Controller Internal Interfaces The peripheral bus interface supports the transfer of 16-bit wide data and is used by the processor in the support of register and FIFO buffer reads and writes. The register block contains all control and status bits and reflects what can be written or read as outlined by the programmer’s model.
Page 666: Description Of Operation
Description of Operation Description of Operation The following sections describe the operation of the TWI interface. TWI Transfer Protocols The TWI controller follows the transfer protocol of the Philips I C Bus Specification version 2.1 dated January 2000. A simple complete transfer is diagrammed in Figure 11-2.
Page 667: Bus Arbitration
Two Wire Interface Controller If multiple clocks attempt to drive the serial clock line, the TWI controller synchronizes its clock with the other remaining clocks. This is shown in Figure 11-4. HIGH COUNT COUNT TWI CONTROLLER CLOCK SECOND MASTER CLOCK RESULT Figure 11-4.
Page 668: Start And Stop Conditions
Description of Operation SCL (BUS) TWI CONTROLLER DATA SECOND MASTER DATA SDA (BUS) ARBITRATION LOST START Figure 11-5. TWI Bus Arbitration The TWI controller monitors the serial data bus (SDA) while is high and if SDA is determined to be an active logic 0 level while the TWI con- troller’s data is a logic 1 level, the TWI controller has lost arbitration and ends generation of clock and data.
Page 669: General Call Support
Two Wire Interface Controller The TWI controller’s special case start and stop conditions include: • TWI controller addressed as a slave-receiver If the master asserts a stop condition during the data phase of a transfer, the TWI controller concludes the transfer ( SCOMP •...
Page 670: Fast Mode
TWI General Operation Fast Mode Fast mode essentially uses the same mechanics as standard mode of opera- tion. It is the electrical specifications and timing that are most effected. When fast mode is enabled ( ) the following timings are modified to FAST meet the electrical requirements.
Page 671: Clock Signal
Two Wire Interface Controller For either master and/or slave mode of operation, the TWI controller is enabled by setting the bit in the register. It is recom- TWI_ENA TWI_CONTROL mended that this bit be set at the time is initialized and remain PRESCALE set.
Page 672: Error Signals And Flags
TWI General Operation The clock low field of the register number of internal time ref- TWI_CLKDIV erence periods the serial clock ( ) is held low. It is represented as an 8-bit binary value. Error Signals and Flags The following sections describe the TWI error signals and flags. TWI Master Status The TWI master mode status register ( ) holds informa-...
Page 673 Two Wire Interface Controller [1] An active “zero” is currently being sensed on the serial clock. The source of the active driver is not known and can be internal or external. [0] An inactive “one” is currently being sensed on the serial clock. •...
Page 674 TWI General Operation • Data not acknowledged ( DNAK [1] The current master transfer was aborted due to the detection of a NAK during data transmission. This bit is W1C. [0] The current master receive has not detected a NAK during data transmission.
Page 675: Twi Slave Status
Two Wire Interface Controller TWI Slave Status During and at the conclusion of slave mode transfers, the TWI slave mode status register ( ) holds information on the current trans- TWI_SLAVE_STAT fer. Generally slave mode status bits are not associated with the generation of interrupts.
Page 676: Twi Fifo Status
TWI General Operation TWI FIFO Status The fields in the TWI FIFO status register ( ) indicate the TWI_FIFO_STAT state of the FIFO buffers’ receive and transmit contents. The FIFO buffers do not discriminate between master data and slave data. By using the sta- tus and control bits provided, the FIFO can be managed to allow simultaneous master and slave operation.
Page 677: Twi Interrupt Status
Two Wire Interface Controller • Transmit FIFO status ( XMTSTAT[1:0] field is read only. It indicates the number of valid data XMTSTAT bytes in the FIFO buffer. The status is updated with each FIFO buffer write using the peripheral data bus or read access by the transmit shift register.
Page 678 TWI General Operation • Transmit FIFO service ( XMTSERV in the register is 0, this bit is set each XMTINTLEN TWI_FIFO_CTL time the field in the register is updated to XMTSTAT TWI_FIFO_STAT either 01 or 00. If is 1, this bit is set each time XMTINTLEN XMTSTAT is updated to 00.
Page 679 Two Wire Interface Controller • Slave transfer error ( SERR [1] A slave error has occurred. A restart or stop condition has occurred during the data receive phase of a transfer. [0] No errors have been detected. • Slave transfer complete ( SCOMP [1] The transfer is complete and either a stop, or a restart was detected.
Page 680: Functional Description
Functional Description Functional Description The following sections describe the functional operation of the TWI. General Setup General setup refers to register writes that are required for both slave mode operation and master mode operation. General setup should be per- formed before either the master or slave enable bits are set. •...
Page 681 Two Wire Interface Controller 3. Program . Enable bits are associated with the desired TWI_INT_MASK interrupt sources. As an example, programming the value 0x000F results in an interrupt output to the processor in the event that a valid address match is detected, a valid slave transfer completes, a slave transfer has an error, a subsequent transfer has begun yet the previous transfer has not been serviced.
Page 682: Master Mode Clock Setup
Functional Description Master Mode Clock Setup Master mode operation is set up and executed on a per-transfer basis. An example of programming steps for a receive and for a transmit are given separately in following sections. The clock setup programming step listed here is common to both transfer types.
Page 683: Master Mode Receive
Two Wire Interface Controller Table 11-3 shows what the interaction between the TWI controller and the processor might look like using this example. Table 11-3. Master Mode Transmit Setup Interaction TWI Controller Master Processor Interrupt: XMTEMPTY – Transmit buffer is Write transmit FIFO buffer.
Page 684: Repeated Start Condition
Functional Description Table 11-4. Master Mode Receive Setup Interaction TWI Controller Master Processor Interrupt: RCVFULL – Receive buffer is full. Read receive FIFO buffer. Acknowledge: Clear interrupt source bits. Interrupt: MCOMP – Master transfer com- Acknowledge: Clear interrupt source bits. plete.
Page 685 Two Wire Interface Controller The tasks performed at each interrupt are: • interrupt XMTSERV This interrupt was generated due to a FIFO access. Since this is the last byte of this transfer, would indicate the transmit FIFO_STATUS FIFO is empty. When read, would be zero.
Page 686: Receive/Transmit Repeated Start Sequence
Functional Description Receive/Transmit Repeated Start Sequence Figure 11-8 illustrates a repeated start data receive followed by a data transmit sequence. 7-BIT ADDRESS 8-BIT DATA NACK 7-BIT ADDRESS 8-BIT DATA XMTSERV INTERRUPT RCVSERV INTERRUPT MCOMP INTERRUPT MCOMP INTERRUPT SHADING INDICATES SLAVE HAS THE BUS Figure 11-8.
Page 687 Two Wire Interface Controller • interrupt XMTSERV This interrupt is generated due to a FIFO access. Simple data han- dling is all that is required. • interrupt MCOMP The transfer is complete. ADSP-BF537 Blackfin Processor Hardware Reference 11-27...
Page 688: Programming Model
Programming Model Programming Model Figure 11-9 Figure 11-10 illustrate the programming model for the TWI. WRITE TO TWI_CONTROL TO SET PRESCALE AND ENABLE THE TWI WRITE TO TWI_SLAVE_ADDR WRITE TO TWI_XMT_DATA REGISTER TO PRE-LOAD THE TX FIFO WRITE TO TWI_FIFO_CTL TO SELECT WHETHER 1 OR 2 BYTES GENERATE INTERRUPTS WRITE TO TWI_INT_MASK TO UNMASK TWI EVENTS TO GENERATE INTERRUPTS...
Page 689 Two Wire Interface Controller WRITE TO TWI_CONTROL TO SET PRESCALE AND ENABLE THE TWI WRITE TO TWI_CLK_DIV WRITE TO TWI_MASTER_ADDR WITH THE ADDRESS OF THE TARGETED DEVICE WRITE TO TWI_FIFO_CTL TO SELECT WHETHER 1 OR 2 BYTES GENERATE INTERRUPTS WRITE TO TWI_INT_MASK TO UNMASK TWI EVENTS TO GENERATE INTERRUPTS WRITE TO TWI_SLAVE_CTL TO ENABLE SLAVE FUNCTIONALITY...
Page 690: Register Descriptions
Register Descriptions Register Descriptions The TWI controller has 16 registers described in the following sections. Figure 11-11 through Figure 11-28 on page 11-47 illustrate the registers. TWI_CONTROL Register TWI Control Register (TWI_CONTROL) 15 14 13 12 11 10 0xFFC0 1404 Reset = 0x0000 SCCB PRESCALE[6:0]...
Page 691: Twi_Slave_Ctl Register
Two Wire Interface Controller TWI_SLAVE_CTL Register The TWI slave mode control register ( ) controls the logic TWI_SLAVE_CTL associated with slave mode operation. Settings in this register do not affect master mode operation and should not be modified to control master mode functionality.
Page 692 Register Descriptions • NAK ( [1] Slave receive transfers generate a data NAK (not acknowledge) at the conclusion of a data transfer. The slave is still considered to be addressed. [0] Slave receive transfers generate an ACK at the conclusion of a data transfer.
Page 693: Twi_Slave_Addr Register
Two Wire Interface Controller TWI_SLAVE_ADDR Register The TWI slave mode address register ( ) holds the slave TWI_SLAVE_ADDR mode address, which is the valid address that the slave-enabled TWI con- troller responds to. The TWI controller compares this value with the received address during the addressing phase of a transfer.
Page 694: Twi_Master_Ctl Register
Register Descriptions TWI_MASTER_CTL Register The TWI master mode control register ( ) controls the TWI_MASTER_CTL logic associated with master mode operation. Bits in this register do not affect slave mode operation and should not be modified to control slave mode functionality. TWI Master Mode Control Register (TWI_MASTER_CTL) 15 14 13 12 11 10 Reset = 0x0000...
Page 695 Two Wire Interface Controller • Serial data (SDA) override ( SDAOVR This bit can be used when direct control of the serial data line is required. Normal master and slave mode operation should not require override operation. [1] Serial data output is driven to an active 0 level overriding all other logic.
Page 696 Register Descriptions • Issue stop condition ( STOP [1] The transfer concludes as soon as possible avoiding any error conditions (as if data transfer count had been reached) and at that time the TWI interrupt mask register ( ) is updated TWI_INT_MASK along with any associated status bits.
Page 697: Twi_Master_Addr Register
Two Wire Interface Controller TWI_MASTER_ADDR Register During the addressing phase of a transfer, the TWI controller, with its master enabled, transmits the contents of the TWI master mode address register ( ). When programming this register, omit the TWI_MASTER_ADDR read/write bit. That is, only the upper 7 bits that make up the slave address should be written to this register.
Page 698: Twi_Master_Stat Register
Register Descriptions TWI_MASTER_STAT Register TWI Master Mode Status Register (TWI_MASTER_STAT) 15 14 13 12 11 10 0xFFC0 1418 Reset = 0x0000 MPROG (Master Transfer BUSBUSY (Bus Busy) - RO in Progress) - RO SCLSEN (Serial Clock Sense) - RO LOSTARB (Lost Arbitration) - SDASEN (Serial Data Sense) - RO BUFWRERR (Buffer Write Error) - W1C ANAK (Address Not...
Page 699 Two Wire Interface Controller Additional information for the register bits includes: TWI_FIFO_CTL • Receive buffer interrupt length ( RCVINTLEN This bit determines the rate at which receive buffer interrupts are to be generated. Interrupts may be generated with each byte received or after two bytes are received.
Page 700: Twi_Fifo_Stat Register
Register Descriptions • Transmit buffer flush ( XMTFLUSH [1] Flush the contents of the transmit buffer and update the status bit to indicate the buffer is empty. This state is held XMTSTAT until this bit is cleared. During an active transmit the transmit buffer in this state responds as if the transmit buffer is empty.
Page 701 Two Wire Interface Controller TWI Interrupt Mask Register (TWI_INT_MASK) For all bits, 0 = Interrupt generation disabled, 1 = Interrupt generation enabled. 15 14 13 12 11 10 0xFFC0 1424 Reset = 0x0000 SINITM (Slave Transfer RCVSERVM (Receive FIFO Initiated Interrupt Mask) Service Interrupt Mask) SCOMPM (Slave Transfer XMTSERVM (Transmit FIFO...
Page 702 Register Descriptions • Master transfer error interrupt mask ( MERRM [1] The corresponding interrupt source is prevented from asserting the interrupt output. [0] A contents of 1 in the corresponding interrupt source results in asserting the interrupt output. • Master transfer complete interrupt mask ( MCOMPM [1] The corresponding interrupt source is prevented from asserting the interrupt output.
Page 703: Twi_Int_Stat Register
Two Wire Interface Controller • Slave transfer complete interrupt mask ( SCOMPM [1] The corresponding interrupt source is prevented from asserting the interrupt output. [0] A contents of 1 in the corresponding interrupt source results in asserting the interrupt output. •...
Page 704: Twi_Xmt_Data16 Register
Register Descriptions Although peripheral bus writes are 16 bits, a write access to adds only one transmit data byte to the FIFO buffer. With TWI_XMT_DATA8 each access, the transmit status ( ) field in the regis- XMTSTAT TWI_FIFO_STAT ter is updated. If an access is performed while the FIFO buffer is full, the write is ignored and the existing FIFO buffer data and its status remains unchanged.
Page 705: Twi_Rcv_Data8 Register
Two Wire Interface Controller register is updated. If an access is performed while the FIFO buffer is not empty, the write is ignored and the existing FIFO buffer data and its sta- tus remains unchanged. DATA IN REGISTER Figure 11-24. Little Endian Byte Order TWI FIFO Transmit Data Double Byte Register (TWI_XMT_DATA16) All bits are WO.
Page 706: Twi_Rcv_Data16 Register
Register Descriptions receive status ( ) field in the register is updated. If RCVSTAT TWI_FIFO_STAT an access is performed while the FIFO buffer is empty, the data is unknown and the FIFO buffer status remains indicating it is empty. TWI FIFO Receive Data Single Byte Register (TWI_RCV_DATA8) All bits are RO.
Page 707: Programming Examples
Two Wire Interface Controller TWI FIFO Receive Data Double Byte Register (TWI_RCV_DATA16) All bits are WO. 15 14 13 12 11 10 0xFFC0 148C Reset = 0x0000 RCVDATA16[15:0] (Receive FIFO 16-Bit Data) Figure 11-28. TWI FIFO Receive Data Double Byte Register Programming Examples The following sections include programming examples for general setup, slave mode, and master mode, as well as guidance for repeated start...
Page 708 Programming Examples .byte rcvFirstWord[2]; .SECTION program; _main: /*********************************************************** TWI Master Initialization subroutine ***********************************************************/ TWI_INIT: /*********************************************************** Enable the TWI controller and set the Prescale value Prescale = 10 (0xA) for an SCLK = 100 MHz (CLKIN = 50MHz) Prescale = SCLK / 10 MHz P1 points to the base of the system MMRs ***********************************************************/ R1 = TWI_ENA | 0xA (z);...
Page 709 Two Wire Interface Controller R1 = RCVSERV | XMTSERV | MERR | MCOMP (z); W[P1 + LO(TWI_INT_MASK)] = R1; /*********************************************************** The address needs to be shifted one place to the right e.g., 1010 001x becomes 0101 0001 (0x51) the TWI controller will actually send out 1010 001x where x is either a 0 for writes or 1 for reads ***********************************************************/...
Page 710 Programming Examples R1 = W[P1 + LO(TWI_FIFO_STAT)](Z); R0 = 0xC; R1 = R1 & R0; CC = R1 == R0; IF !cc jump Rx_stat; R0 = W[P1 + LO(TWI_RCV_DATA16)](Z); /* Read data from the RX fifo ssync; /*********************************************************** check that master transfer has completed MCOMP will be set when Count reaches zero ***********************************************************/ M_COMP:...
Page 711 Two Wire Interface Controller Program the Master Control register with: 1. the number of bytes to transfer: TWICount(x) 2. Repeated Start (RESTART): optional 3. speed mode: FAST or Standard 4. direction of transfer: MDIR = 1 for reads, MDIR = 0 for writes 5.
Page 712: Slave Mode Setup
Programming Examples W[P1 + LO(TWI_XMT_DATA8)] = R3; Loop_End: SSYNC; /* check that master transfer has completed */ M_COMP: R1 = W[P1 + LO(TWI_INT_STAT)](z); CC = BITTST (R1, bitpos(MCOMP)); if !CC jump M_COMP; M_COMP.END:W[P1 + LO(TWI_INT_STAT)] = R1; idle; _main.end: Slave Mode Setup Listing 11-2 shows how to configure the slave for interrupt based trans- fers.
Page 713 Two Wire Interface Controller .BYTE TWI_TX[file_size] = "transmit.dat"; .section L1_code; _main: /*********************************************************** TWI Slave Initialization subroutine ***********************************************************/ TWI_SLAVE_INIT: /*********************************************************** Enable the TWI controller and set the Prescale value Prescale = 10 (0xA) for an SCLK = 100 MHz (CLKIN = 50MHz) Prescale = SCLK / 10 MHz P1 points to the base of the system MMRs P0 points to the base of the core MMRs...
Page 714 Programming Examples W[P1 + LO(TWI_XMT_DATA16)] = R3; /*********************************************************** FIFO Control determines whether an interrupt is generated for every byte transferred or for every two bytes. A value of zero which is the default, allows for single byte events to generate interrupts ***********************************************************/ R1 = 0;...
Page 715 Two Wire Interface Controller /*********************************************************** Remap the vector table pointer from the default __I10HANDLER to the new _TWI_ISR interrupt service routine ***********************************************************/ R1.H = HI(_TWI_ISR); R1.L = LO(_TWI_ISR); [P0 + LO(EVT10)] = R1; /* note that P0 points to the base of the core MMR registers */ /*********************************************************** ENABLE TWI generate to interrupts at the system level...
Page 716 Programming Examples Listing 11-3. TWI Slave Interrupt Service Routine /*********************************************************** Function: _TWI_ISR Description: This ISR is executed when the TWI controller detects a slave initiated transfer. After an interrupt is ser- viced, its corresponding bit is cleared in the TWI_INT_STAT register.
Page 717 Two Wire Interface Controller RECEIVE: CC = BITTST(R1, BITPOS(RCVSERV)); if !CC JUMP TRANSMIT; R0 = W[P1 + LO(TWI_RCV_DATA8)] (Z); /* read data */ B[P2++] = R0 ; /* store bytes into a buffer pointed to by P2 */ R0 = RCVSERV(Z); W[P1 + LO(TWI_INT_STAT)] = R0;...
Page 718 Programming Examples /*********************************************************** slave overflow ***********************************************************/ SlaveOverflow: CC = BITTST(R1, BITPOS(SOVF)); if !CC JUMP SlaveTransferComplete; R0 = SOVF(Z); W[P1 + LO(TWI_INT_STAT)] = R0; /* clear interrupt source bit */ ssync; JUMP _TWI_ISR.END; /* exit */ /*********************************************************** slave transfer complete ***********************************************************/ SlaveTransferComplete: CC = BITTST(R1, BITPOS(SCOMP));...
Page 719: Electrical Specifications
Two Wire Interface Controller Electrical Specifications All logic complies with the Electrical Specification outlined in the Philips C Bus Specification version 2.1 dated January 2000. ADSP-BF537 Blackfin Processor Hardware Reference 11-59...
Page 720 Electrical Specifications 11-60 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 721: Overview
12 SPORT CONTROLLERS This chapter describes the synchronous Serial peripheral Port (SPORT). Following an overview and a list of key features is a description of opera- tion and functional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples.
Page 722: Features
Overview between two or more processors in a multiprocessor system. Many proces- sors provide compatible interfaces, including DSPs from Analog Devices and other manufacturers. Both SPORTs have the same capabilities and are programmed in the same way. Each SPORT has its own set of control registers and data buffers.
Page 723: Interface Overview
SPORT Controllers • Internally generates serial clock and frame sync signals in a wide range of frequencies or accepts clock and frame sync input from an external source. • Operates with or without frame synchronization signals for each data word, with internally generated or externally generated frame signals, with active high or active low frame signals, and with either of two configurable pulse widths and frame signal timing.
Page 724 Interface Overview of signals for receive. The receive and transmit functions are programmed separately. Each SPORT is a full duplex device, capable of simultaneous data transfer in both directions. The SPORTs can be programmed for bit rate, frame sync, and number of bits per word by writing to mem- ory-mapped registers.
Page 725 SPORT Controllers If the secondary data signals of SPORT1 are not used, 10-bit PPI opera- tion is enabled by keeping the bit cleared. The SPORT1 transmit PGSE channel remains fully functional, even when the PPI operates up to 13-bit mode and the bit is cleared.
Page 726 Interface Overview Tx REGISTER Rx REGISTER Tx FIFO Rx FIFO 4 x 32 OR 8 x 16 4 x 32 OR 8 x 16 SERIAL Tx PRI Tx SEC Rx PRI Rx SEC CONTROL HOLD REG HOLD REG HOLD REG HOLD REG COMPANDING COMPANDING...
Page 727 SPORT Controllers The primary and secondary data pins, if enabled by the port configura- tion, provide a method to increase the data throughput of the serial port. They do not behave as totally separate SPORTs; rather, they operate in a synchronous manner (sharing clock and frame sync) but on separate data.
Page 728 Interface Overview BLACKFIN PORT J SPORT0 TSCLK0 PJ10 TFS0 RSCLK0 RFS0 SERIAL PJ11 DT0PRI DEVICE A DR0PRI (PRIMARY) SERIAL DT0SEC DEVICE B DR0SEC (SECONDARY) SPORT1 PORT G TSCLK1 PG13 TFS1 PG14 PG10 RSCLK1 PG11 RFS1 SERIAL DT1PRI PG15 DEVICE C PG12 DR1PRI (PRIMARY)
Page 729: Sport Pin/Line Terminations
SPORT Controllers Figure 12-3 shows an example of a stereo serial device with three transmit and two receive channels connected to the processor. AD1836 STEREO SERIAL BLACKFIN DEVICE PORT J SPORT0 DLRCLK TSCLK0 DBCLK TFS0 PJ10 RSCLK0 DSDATA1 DSDATA2 RFS0 DSDATA3 DT0PRI PJ11...
Page 730: Description Of Operation
Description of Operation Description of Operation SPORT Operation This section describes general SPORT operation, illustrating the most common use of a SPORT. Since the SPORT functionality is configurable, this description represents just one of many possible configurations. Writing to a SPORT’s register readies the SPORT for trans- SPORTx_TX mission.
Page 731: Setting Sport Modes
SPORT Controllers A processor reset disables the SPORTs by clearing the SPORTx_TCR1 , and registers (including the SPORTx_TCR2 SPORTx_RCR1 SPORTx_RCR2 enable bits) and the TSPEN RSPEN SPORTx_TCLKDIV SPORTx_RCLKDIV , and clock and frame sync divisor regis- SPORTx_TFSDIVx SPORTx_RFSDIVx ters. Any ongoing operations are aborted. Clearing the enable bits disables the SPORTs and aborts TSPEN...
Page 732: Stereo Serial Operation
Description of Operation Each SPORT has its own set of control registers and data buffers. These registers are described in detail in the “SPORT Registers” section. All con- trol and status bits in the SPORT registers are active high unless otherwise noted.
Page 733 SPORT Controllers Table 12-2. Stereo Serial Settings (Cont’d) Bit Field Stereo Audio Serial Scheme Left-Justified DSP Mode RCKFE SLEN 2 – 31 2 – 31 2 – 31 RLSBIT RFSDIV 2 – Max 2 – Max 2 – Max (If internal FS is selected.) RXSE (Secondary Enable is available for RX and TX.) Note most bits shown as a 0 or 1 may be changed depending on the user’s...
Page 734 Description of Operation The secondary pins are useful extensions of the DRxSEC DTxSEC SPORT which pair well with stereo serial mode. Multiple I S streams of data can be transmitted or received using a single SPORT. Note the pri- mary and secondary pins are synchronous, as they share clock and LRCLK (frame sync) pins.
Page 735: Multichannel Operation
SPORT Controllers RIGHT CHANNEL LEFT CHANNEL RSCLKx DRxPRI LEFT-JUSTIFIED MODE—3 TO 32 BITS PER CHANNEL LEFT CHANNEL RIGHT CHANNEL RSCLKx DRxPRI S MODE—3 TO 32 BITS PER CHANNEL RSCLKx DRxPRI DSP MODE—3 TO 32 BITS PER CHANNEL NOTES: 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2.
Page 736 Description of Operation total channels. RX and TX must use the same 128-channel region to selec- tively enable channels. The SPORT can do any of the following on each channel: • Transmit data • Receive data • Transmit and receive data •...
Page 737 SPORT Controllers Figure 12-6 shows example timing for a multichannel transfer that has these characteristics: • Use TDM method where serial data is sent or received on different channels sharing the same serial bus • Can independently select transmit and receive channels •...
Page 738: Multichannel Enable
Description of Operation Multichannel Enable Setting the bit in the register enables multichannel MCMEN SPORTx_MCM2 mode. When , multichannel operation is enabled; when MCMEN = 1 , all multichannel operations are disabled. MCMEN = 0 Setting the bit enables multichannel operation for both the MCMEN receive and transmit sides of the SPORT.
Page 739: Frame Syncs In Multichannel Mode
SPORT Controllers Table 12-3. Multichannel Mode Configuration (Cont’d) SPORTx_RCR1 or SPORTx_TCR1 or Notes SPORTx_RCR2 SPORTx_TCR2 RCKFE TCKFE Set or clear both to same value SLEN SLEN Set or clear both to same value RXSE TXSE Independent RSFSE TSFSE Both must be 0 RRFST TRFST Ignored...
Page 740: The Multichannel Frame
Description of Operation signal is used as a transmit data valid signal which is active during transmission of an enabled word. The SPORT’s data transmit pin is three-stated when the time slot is not active, and the signal serves as an output-enabled signal for the data transmit pin.
Page 741: Multichannel Frame Delay
SPORT Controllers RSCLK FRAME SYNC CHANNEL DATA DATA IGNORED DATA IGNORED DATA IGNORED MULTICHANNEL FRAME SPx_MCMC REG FIELD: WINDOW WINDOW OFFSET SIZE UNITS: BITS WORDS MULTIPLES OF 8 WORDS RANGE: 0–15 0–1015 8–128 NOTE: FRAME LENGTH IS SET BY FRAME SYNC DIVIDE OR EXTERNAL FRAME SYNC PERIOD. Figure 12-7.
Page 742: Window Offset
Description of Operation increments of 8; the default value of 0 corresponds to a minimum active window size of 8 channels. To calculate the active window size from the register, use this equation: WSIZE Number of words in active window = 8 x (WSIZE + 1) Since the DMA buffer size is always fixed, it is possible to define a smaller window size (for example, 32 words), resulting in a smaller DMA buffer size (in this example, 32 words instead of 128 words) to save DMA band-...
Page 743: Channel Selection Register
SPORT Controllers Normally (When ), the data is transmitted on the same edge that FSDR = 0 is generated. For example, a positive edge on causes data to be transmitted on the positive edge of the —either the same edge or the TSCLK following one, depending on when is set.
Page 744: Multichannel Dma Data Packing
Description of Operation Channel select bit 0 always corresponds to the first word of the active win- dow. To determine a channel’s absolute position in the frame, add the window offset words to the channel select position. For example, setting bit 7 in selects word 71 of the active window to be enabled.
Page 745: Support For H.100 Standard Protocol
SPORT Controllers If the bits are cleared (the default, indicating that data is not packed), the SPORT expects the DMA buffer to have a word for each of the channels in the active window, whether enabled or not, so the DMA buffer size must be equal to the size of the window.
Page 746: X Clock Recovery Control
Functional Description 2X Clock Recovery Control The SPORTs can recover the data rate clock from a provided 2X input clock. This enables the implementation of H.100 compatibility modes for MVIP-90 (2 Mbps data) and HMVIP (8 Mbps data), by recovering 2 MHz from 4 MHz or 8 MHz from the 16 MHz incoming clock with the proper phase relationship.
Page 747 SPORT Controllers When an internal frame sync is selected ( in the reg- ITFS SPORTx_TCR1 ister or in the register) and frame syncs are not IRFS SPORTx_RCR1 required, the first frame sync does not update the clock divider if the value has changed.
Page 748: Maximum Clock Rate Restrictions
Functional Description Maximum Clock Rate Restrictions Externally generated late transmit frame syncs also experience a delay from arrival to data output, and this can limit the maximum serial clock speed. See the product data sheet for exact timing specifications. Word Length Each SPORT channel (transmit and receive) independently handles word lengths of 3 to 32 bits.
Page 749: Companding
SPORT Controllers Table 12-4. TDTYPE, RDTYPE, and Data Formatting TDTYPE or SPORTx_TCR1 Data Formatting SPORTx_RCR1 Data Formatting RDTYPE Normal operation Zero fill Reserved Sign extend Compand using μ-law Compand using μ-law Compand using A-law Compand using A-law These formats are applied to serial data words loaded into the SPORTx_RX buffers.
Page 750: Clock Signal Options
Functional Description Clock Signal Options Each SPORT has a transmit clock signal ( ) and a receive clock signal TSCLK ). The clock signals are configured by the bits of RSCLK TCKFE RCKFE registers. Serial clock frequency is con- SPORTx_TCR1 SPORTx_RCR1 figured in the registers.
Page 751: Framed Versus Unframed
SPORT Controllers Framed Versus Unframed The use of multiple frame sync signals is optional in SPORT communica- tions. The (transmit frame sync required select) and (receive TFSR RFSR frame sync required select) control bits determine whether frame sync sig- nals are required. These bits are located in the SPORTx_TCR1 registers.
Page 752: Internal Versus External Frame Syncs
Functional Description TSCLK RSCLK FRAMED DATA UNFRAMED DATA DATA Figure 12-9. Framed Versus Unframed Data Internal Versus External Frame Syncs Both transmit and receive frame syncs can be independently generated internally or can be input from an external source. The bits ITFS IRFS...
Page 753: Active Low Versus Active High Frame Syncs
SPORT Controllers Active Low Versus Active High Frame Syncs Frame sync signals may be either active high or active low (in other words, inverted). The bits of the LTFS LRFS SPORTx_TCR1 SPORTx_RCR1 registers determine frame sync logic levels: • When , the corresponding frame sync signal LTFS LRFS...
Page 754 Functional Description Note externally generated data and frame sync signals should change state on the opposite edge than that selected for sampling. For example, for an externally generated frame sync to be sampled on the rising edge of the clock ( in the reg- TCKFE = 1...
Page 755 SPORT Controllers DRIVE SAMPLE EDGE EDGE TSCLK = RSCLK INTERNAL OR EXTERNAL TFS = RFS INTERNAL OR EXTERNAL Figure 12-11. Example of TCKFE = RCKFE = 1, Transmit and Receive Connected Early Versus Late Frame Syncs (Normal Versus Alternate Timing) Frame sync signals can occur during the first bit of each data word (late) or during the serial clock cycle immediately preceding the first bit (early).
Page 756 Functional Description When , late frame syncs are configured; this is the LATFS = 1 LARFS alternate mode of operation. In this mode, the first bit of the transmit data word is available and the first bit of the receive data word is sampled in the same serial clock cycle that the frame sync is asserted.
Page 757: Data Independent Transmit Frame Sync
SPORT Controllers xSCLK LATE FRAME SYNC EARLY FRAME SYNC DATA Figure 12-12. Normal Versus Alternate Framing Data Independent Transmit Frame Sync Normally the internally generated transmit frame sync signal ( ) is out- put only when the buffer has data ready to transmit. The SPORTx_TX data-independent transmit frame sync select bit ( allows the contin-...
Page 758: Moving Data Between Sports And Memory
Functional Description If the internally generated is used, a single write to the data SPORTx_TX register is required to start the transfer. Moving Data Between SPORTs and Memory Transmit and receive data can be transferred between the SPORTs and on-chip memory in one of two ways: with single word transfers or with DMA block transfers.
Page 759: Pab Errors
SPORT Controllers PAB Errors The SPORT generates a PAB error for illegal register read or write opera- tions. Examples include: • Reading a write-only register (for example, SPORT_TX • Writing a read-only register (for example, SPORT_RX • Writing or reading a register with the wrong size (for example, 32-bit read of a 16-bit register) •...
Page 760 Functional Description Figure 12-13 Figure 12-14, the normal framing mode is shown for non-continuous data (any number of cycles between TSCLK RSCLK words) and continuous data (no cycles between words). TSCLK SCLK RSCLK RFS OUTPUT RFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN.
Page 761 SPORT Controllers the output meets the input timing requirement; therefore, with two SPORT channels used, one SPORT channel could provide for the other SPORT channel. RSCLK RFS OUTPUT RFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN. DR REPRESENTS DRxPRI AND/OR DRxSEC, DEPENDING ON DESIRED CONFIGURATION.
Page 762 Functional Description before the first bit (in normal mode) or at the same time as the first RSCLK bit (in alternate mode). This mode is appropriate for multiword bursts (continuous reception). RSCLK DR REPRESENTS DRxPRI AND/OR DRxSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 12-17.
Page 763 SPORT Controllers Figure 12-22 show non-continuous and continuous transmission in the alternate framing mode. As noted previously for the receive timing dia- grams, the output meets the input timing requirement. TSCLK TFS OUTPUT TFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN. DT REPRESENTS DTxPRI AND/OR DTxSEC, DEPENDING ON DESIRED CONFIGURATION.
Page 764 Functional Description TSCLK TFS OUTPUT TFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN. DT REPRESENTS DTxPRI AND/OR DTxSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 12-21. SPORT Transmit, Alternate Framing TSCLK TFS OUTPUT TFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTxPRI AND/OR DTxSEC, DEPENDING ON DESIRED CONFIGURATION.
Page 765: Sport Registers
SPORT Controllers TSCLK DT REPRESENTS DTxPRI AND/OR DTxSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 12-23. SPORT Transmit, Unframed Mode, Normal Framing TSCLK DT REPRESENTS DTxPRI AND/OR DTxSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 12-24. SPORT Transmit, Unframed Mode, Alternate Framing SPORT Registers The following sections describe the SPORT registers.
Page 766 SPORT Registers Table 12-5. SPORT Register Mapping (Cont’d) Register Name Function Notes SPORTx_TFSDIV Transmit frame Ignored if external frame sync mode is selected sync divider regis- SPORTx_TX SPORT transmit See description of FIFO buffering at data register “SPORTx_TX Register” on page 12-58 SPORTx_RCR1 Primary receive Bits [15:1] can only be written if bit 0 = 0...
Page 767: Register Writes And Effective Latency
SPORT Controllers Register Writes and Effective Latency When the SPORT is disabled ( cleared), SPORT register TSPEN RSPEN writes are internally completed at the end of the cycle in which they SCLK occurred, and the register reads back the newly-written value on the next cycle.
Page 768 SPORT Registers When the SPORT is enabled to transmit ( set), corresponding TSPEN SPORT configuration register writes are not allowed except for and multichannel mode channel select registers. Writes to SPORTx_TCLKDIV disallowed registers have no effect. While the SPORT is enabled, is not written except for bit 0 ( ).
Page 769 SPORT Controllers SPORTx Transmit Configuration 2 Register (SPORTx_TCR2) 15 14 13 12 11 10 SPORT0: 0xFFC0 0804 Reset = 0x0000 SPORT1: 0xFFC0 0904 SLEN[4:0] (SPORT Word Length) TRFST (Left/Right Order) 0 - Left stereo channel first 00000 - Illegal value 1 - Right stereo channel first 00001 - Illegal value Serial word length is value in...
Page 770 SPORT Registers Clearing causes the SPORT to stop driving data, , and TSPEN TSCLK frame sync pins; it also shuts down the internal SPORT circuitry. In low power applications, battery life can be extended by clearing whenever the SPORT is not in use. TSPEN All SPORT control registers should be programmed before TSPEN...
Page 771 SPORT Controllers instruction; the field tells the SPORT how many of those bits SLEN to shift out of the register over the serial link. The SPORT always transfers the lower bits from the transmit buffer. SLEN+1 The frame sync signal is controlled by the SPORTx_TFSDIV registers, not by .
Page 772: Sportx_Rcr1 And Sportx_Rcr2 Registers
SPORT Registers register on time. If the receiver can tolerate occasional SPORTx_TX late frame sync pulses, should be cleared to prevent the DITFS SPORT from transmitting old data twice or transmitting garbled data if the processor is late in loading the register.
Page 773 SPORT Controllers A SPORT is enabled for receive if bit 0 ( ) of the receive configura- RSPEN tion 1 register is set to 1. This bit is cleared during either a hard reset or a soft reset, disabling all SPORT reception. When the SPORT is enabled to receive ( set), corresponding RSPEN...
Page 774 SPORT Registers SPORTx Receive Configuration 1 Register (SPORTx_RCR1) 15 14 13 12 11 10 SPORT0: 0xFFC0 0820 Reset = 0x0000 SPORT1: 0xFFC0 0920 RCKFE (Clock Falling RSPEN (Receive Enable) Edge Select) 0 - Receive disabled 0 - Drive internal frame sync 1 - Receive enabled on rising edge of RSCLK.
Page 775 SPORT Controllers SPORTx Receive Configuration 2 Register (SPORTx_RCR2) 15 14 13 12 11 10 SPORT0: 0xFFC0 0824 Reset = 0x0000 SPORT1: 0xFFC0 0924 SLEN[4:0] (SPORT Word Length) RRFST (Left/Right Order) 0 - Left stereo channel first 00000 - Illegal value 1 - Right stereo channel first 00001 - Illegal value Serial word length is value in...
Page 776 SPORT Registers All SPORT control registers should be programmed before RSPEN set. Typical SPORT initialization code first writes all control regis- ters, including DMA control if applicable. The last step in the code is to write with all of the necessary bits, including SPORTx_RCR1 RSPEN •...
Page 777: Data Word Formats
SPORT Controllers • Low receive frame sync select. ( ). This bit selects an active low LRFS (if set) or active high (if cleared). • Late receive frame sync. ( ). This bit configures late frame LARFS syncs (if set) or early frame syncs (if cleared). •...
Page 778: Sportx_Tx Register
SPORT Registers SPORTx_TX Register The SPORTx transmit data register ( ) is a write-only register. SPORTx_TX Reads produce a Peripheral Access Bus (PAB) error. Writes to this register cause writes into the transmitter FIFO. The 16-bit wide FIFO is 8 deep for word length <= 16 and 4 deep for word length >...
Page 779 SPORT Controllers When transmit is enabled, data from the FIFO is assembled in the TX Hold register based on , and then shifted into the primary TXSE SLEN and secondary shift registers. From here, the data is shifted out serially on pins.
Page 780: Sportx_Rx Register
SPORT Registers SPORTx Transmit Data Register (SPORTx_TX) SPORT0: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0810 Reset = 0x0000 0000 SPORT1: 0xFFC0 0910 Transmit Data[31:16] 15 14 13 12 11 10 Transmit Data[15:0] Figure 12-30.
Page 781 SPORT Controllers Data storage and data ordering in the FIFO are shown in Figure 12-31. register is shown in Figure 12-32. SPORTx_RX FROM Rx HOLD REGISTER FROM Rx HOLD REGISTER ONLY PRIMARY ENABLED PRIMARY AND PRIMARY SECONDARY DATA LENGTH <= 16 BITS SECONDARY ENABLED PRIMARY PRIMARY...
Page 782 SPORT Registers into the RX hold registers for primary and secondary data, respectively. Data from the hold registers is moved into the FIFO based on RXSE SLEN The SPORT RX interrupt is generated when and the RX FIFO RSPEN = 1 has received words in it.
Page 783: Sportx_Stat Register
SPORT Controllers SPORTx_STAT Register The SPORT status register ( ) is used to determine if the SPORTx_STAT access to a SPORT RX or TX FIFO can be made by determining their full or empty status. This register is shown in Figure 12-33.
Page 784: Sportx_Tclkdiv And Sportx_Rclkdiv Registers
SPORT Registers SPORTx Status Register (SPORTx_STAT) 15 14 13 12 11 10 SPORT0: 0xFFC0 0830 Reset = 0x0040 SPORT1: 0xFFC0 0930 TXHRE (Transmit Hold Register Empty) RXNE (Receive FIFO Not Empty Status) 0 - Not empty 0 - Empty 1 - Empty 1 - Data present in FIFO TOVF (Sticky Transmit Overflow Status) - W1C RUVF (Sticky Receive Under-...
Page 785: Sportx_Tfsdiv And Sportx_Rfsdiv Register
SPORT Controllers SPORTx Receive Serial Clock Divider Register (SPORTx_RCLKDIV) 15 14 13 12 11 10 SPORT0: 0xFFC0 0828 Reset = 0x0000 SPORT1: 0xFFC0 0928 Serial Clock Divide Modulus[15:0] Figure 12-35. SPORTx Receive Serial Clock Divider Register SPORTx_TFSDIV and SPORTx_RFSDIV Register The 16-bit SPORTx transmit frame sync divider register ( SPORTx_TFSDIV and the SPORTx receive frame sync divider register (...
Page 786: Sportx_Mcmcn Registers
SPORT Registers SPORTx Receive Frame Sync Divider Register (SPORTx_RFSDIV) 15 14 13 12 11 10 SPORT0: Reset = 0x0000 0xFFC0 082C SPORT1: 0xFFC0 092C Frame Sync Divider[15:0] Number of receive clock cycles counted before gener- ating RFS pulse Figure 12-37. SPORTx Receive Frame Sync Divider Register SPORTx_MCMCn Registers There are two SPORTx multichannel configuration registers ) for each SPORT, shown in...
Page 787: Sportx_Chnl Register
SPORT Controllers SPORTx Multichannel Configuration Register 2 (SPORTx_MCMC2) 15 14 13 12 11 10 SPORT0: Reset = 0x0000 0xFFC0 083C SPORT1: 0xFFC0 093C MFD[3:0] (Multichannel MCCRM[1:0] (2X Clock Frame Delay) Recovery Mode) 0x - Bypass mode Delay between frame sync pulse and the 10 - Recover 2 MHz clock first data bit in Multichannel mode from 4 MHz...
Page 788: Sportx_Mrcsn Registers
SPORT Registers Once the window size has completed, the channel counter resets to 0 in preparation for the next frame. Because there are synchronization delays between and the processor clock, the channel register value is RSCLK approximate. It is never ahead of the channel being served, but it may lag behind.
Page 789 SPORT Controllers enabled by the bit, both inputs are processed on enabled channels. RXSE Clearing the bit in the register causes the SPORT to ignore SPORTx_MRCSn the data on either channel. SPORTx Multichannel Receive Select Registers (SPORTx_MRCSn) For all bits, 0 - Channel disabled, 1 - Channel enabled, so SPORT selects that word from multiple word block of data.
Page 790: Sportx_Mtcsn Registers
SPORT Registers Table 12-6. SPORTx Multichannel Receive Select Register Memory-mapped Addresses Register Name Memory-mapped Address SPORT0_MRCS0 0xFFC0 0850 SPORT0_MRCS1 0xFFC0 0854 SPORT0_MRCS2 0xFFC0 0858 SPORT0_MRCS3 0xFFC0 085C SPORT1_MRCS0 0xFFC0 0950 SPORT1_MRCS1 0xFFC0 0954 SPORT1_MRCS2 0xFFC0 0958 SPORT1_MRCS3 0xFFC0 095C SPORTx_MTCSn Registers The multichannel selection registers are used to enable and disable indi- vidual channels.
Page 791 SPORT Controllers word on the enabled channel. Clearing the bit in the regis- SPORTx_MTCSn ter causes both SPORT controllers’ data transmit pins to three-state during the time slot of that channel. SPORTx Multichannel Transmit Select Registers (SPORTx_MTCSn) For all bits, 0 - Channel disabled, 1 - Channel enabled, so SPORT selects that word from multiple word block of data.
Page 792: Programming Examples
Programming Examples Table 12-7. SPORTx Multichannel Transmit Select Register Memory-mapped Addresses Register Name Memory-mapped Address SPORT0_MTCS0 0xFFC0 0840 SPORT0_MTCS1 0xFFC0 0844 SPORT0_MTCS2 0xFFC0 0848 SPORT0_MTCS3 0xFFC0 084C SPORT1_MTCS0 0xFFC0 0940 SPORT1_MTCS1 0xFFC0 0944 SPORT1_MTCS2 0xFFC0 0948 SPORT1_MTCS3 0xFFC0 094C Programming Examples This section shows an example of typical usage of the SPORT peripheral in conjunction with the DMA controller.
Page 793: Sport Initialization Sequence
SPORT Controllers SPORT Initialization Sequence The SPORT’s receiver and transmitter are configured, but they are not enabled yet. Listing 12-1. SPORT Initialization Program_SPORT_TRANSMITTER_Registers: /* Set P0 to SPORT0 Base Address */ P0.h = hi(SPORT0_TCR1); P0.l = lo(SPORT0_TCR1); /* Configure Clock speeds */ R1 = SPORT_TCLK_CONFIG;...
Page 794 Programming Examples Program_SPORT_RECEIVER_Registers: /* Set P0 to SPORT0 Base Address */ P0.h = hi(SPORT0_RCR1); P0.l = lo(SPORT0_RCR1); /* Configure Clock speeds */ R1 = SPORT_RCLK_CONFIG; /* Divider SCLK/RCLK (value 0 to 65535) */ W[P0 + (SPORT0_RCLKDIV - SPORT0_RCR1)] = R1; RCK divider register */ /* number of Bitclock between FrameSyncs -1...
Page 795: Dma Initialization Sequence
SPORT Controllers DMA Initialization Sequence Next the DMA channels for receive (channel3) and for transmit (channel4) are set up for auto-buffered, one-dimensional, 32-bit transfers. Again, there are other possibilities, so generic labels have been used, with a particular value shown in the comments. See Chapter 5, “Direct Memory Access”, for a detailed explanation of the bits.
Page 796 Programming Examples W[P0 + (DMA3_X_MODIFY - DMA3_CONFIG)] = R1; /* X_modify regis- ter */ /* start_address register points to memory buffer to be filled R1.l = rx_buf; R1.h = rx_buf; [P0 + (DMA3_START_ADDR - DMA3_CONFIG)] = R1; BITSET(R0,0); /* R0 still contains value of CONFIG register - set bit 0 */ W[P0] = R0;...
Page 797: Interrupt Servicing
SPORT Controllers R1.h = tx_buf; [P0 + (DMA4_START_ADDR - DMA4_CONFIG)] = R1; BITSET(R0,0); /* R0 still contains value of CONFIG register - set bit 0 */ W[P0] = R0; /* enable DMA channel (SPORT not enabled yet) */ Interrupt Servicing The receive channel and the transmit channel will each generate an inter- rupt request if so programmed.
Page 798: Starting A Transfer
Programming Examples = 1; W[P0] = R1.l; /* write one to clear RETI = [SP++]; rti; Starting a Transfer After the initialization procedure outlined in the previous sections, the receiver and transmitter are enabled. The core may just wait for interrupts. Listing 12-4.
Page 799: Overview
13 UART PORT CONTROLLERS This chapter describes the Universal Asynchronous Receiver/Transmitter (UART) modules. Following an overview and a list of key features is a description of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview The processor features two separate and identical UART modules.
Page 800: Interface Overview
Interface Overview • SIR IrDA operation mode • Internal loop back The UARTs are logically compliant to EIA-232E, EIA-422, EIA-485 and LIN standards, but usually require external transceiver devices to meet electrical requirements. In IrDA® (Infrared Data Association) mode, the UARTs meet the half-duplex IrDA SIR (9.6/115.2 Kbps rate) protocol.
Page 801: Internal Interface
UART Port Controllers BLACKFIN SIC CONTROLLER DMA CONTROLLER UARTx UARTx_IIR UARTx_DLH UARTx_IER UARTx_DLL UARTx_RBR TRANSCEIVER UARTx_THR UARTx_LSR UARTx_GCTL UARTx_LCR UARTx_SCR UARTx_MCR Figure 13-1. UART Block Diagram Internal Interface The UARTs are DMA-capable peripherals with support for separate TX and RX DMA master channels. They can be used in either DMA or pro- grammed non-DMA mode of operation.
Page 802: Description Of Operation
Description of Operation All UART registers are 8 bits wide. They connect to the PAB bus. How- ever, some registers share their address as controlled by the bit in the DLAB register. The registers also connect to UARTx_LCR UARTx_RBR UARTx_THR the DAB bus Timer 1 provides a hardware assisted autobaud detection mechanism for use with UART 0.
Page 803: Uart Transmit Operation
UART Port Controllers Using the 16x data rate clock, RZI modulation is achieved by inverting and modulating the non-return-to-zero (NRZ) code normally transmitted by the UART. On the receive side, the 16x clock is used to determine an IrDA pulse sample window, from which the RZI-modulated NRZ code is recovered.
Page 804: Uart Receive Operation
Description of Operation When enabled by the bit in the register, a 0 to 1 transi- ETBEI UARTx_IER tion of the flag requests an interrupt on the dedicated output. THRE TXREQ This signal is routed through the DMA controller. If the associated DMA channel is enabled, the signal functions as a DMA request, other- TXREQ...
Page 805 UART Port Controllers If enabled by the bit in the register, a 0 to 1 transition of ERBFI UARTx_IER flag requests an interrupt on the dedicated output. This sig- RXREQ nal is routed through the DMA controller. If the associated DMA channel is enabled, the signal functions as a DMA request, otherwise the RXREQ...
Page 806: Irda Transmit Operation
Description of Operation each start bit, so the error accumulates only over the length of a single word. A receive filter removes spurious pulses of less than two times the sampling clock period. IrDA Transmit Operation To generate the IrDA pulse transmitted by the UART, the normal NRZ output of the transmitter is first inverted if the bit is cleared, so a 0 TPOLC...
Page 807: Irda Receive Operation
UART Port Controllers IrDA Receive Operation The IrDA receiver function is more complex than the transmit function. The receiver must discriminate the IrDA pulse and reject noise. To do this, the receiver looks for the IrDA pulse in a narrow window centered around the middle of the expected pulse.
Page 808: Interrupt Processing
Description of Operation RECEIVED IrDA PULSE IR POL = 1 RECEIVED IrDA PULSE IR POL = 0 8/16 16/16 8/16 16/16 SAMPLING WINDOWN PULSE DETECT OUTPUT RECOVERED NRZ INPUT Figure 13-4. IrDA Receiver Pulse Detection Interrupt Processing Each UART module has three interrupt outputs. One is dedicated for transmission, one for reception, and the third is used to report line status.
Page 809 UART Port Controllers transmit and receive requests cannot be forwarded. Refer to the descrip- tion of the peripheral map registers on page 5-71 in the “Direct Memory Access” chapter. Transmit interrupts are enabled by the bit in the register. ETBEI UARTx_IER If set, the transmit request is asserted when the bit in the...
Page 810: Bit Rate Generation
Description of Operation For legacy reasons, the registers still reflect the UART interrupt UARTx_IIR status. Legacy operation may require bundling all UART interrupt sources to a single interrupt channel and servicing them all by the same software routine. This can be established by globally assigning all UART interrupts to the same interrupt priority, by using the System Interrupt Controller (SIC).
Page 811: Autobaud Detection
UART Port Controllers Table 13-1. UART Bit Rate Examples With 100 MHz SCLK (Cont’d) Bit Rate Actual % Error 38400 38343.56 .147 57600 57339.45 .452 115200 115740.74 .469 921600 892857.14 3.119 6250000 6250000 Careful selection of frequencies, that is, even multiples of SCLK desired bit rates, can result in lower error percentages.
Page 812 Description of Operation detection is performed to prevent the UART from starting reception with incorrect bit rate matching. Alternatively, the UART can be disconnected from the pin by setting the bit. LOOP A software routine can detect the pulse widths of serial stream bit cells. Because the sample base of the timers is synchronous with the UART operation—all derived from —the pulse widths can be used to calcu-...
Page 813: Programming Model
UART Port Controllers For example, predefine ASCII character “@” (0x40) as the autobaud detection character and measure the period between two subsequent fall- ing edges. As shown in Figure 13-6, measure the period between the falling edge of the start bit and the falling edge after bit 6. Since this period encloses 8 bits, apply the formula: DIVISOR = TIMERx_PERIOD >>...
Page 814 Programming Model flag is set when is ready for new data and cleared THRE UARTx_THR when the processor loads new data into . Writing UARTx_THR UARTx_THR when it is not empty overwrites the register with the new value and the previous character is never transmitted.
Page 815: Dma Mode
UART Port Controllers DMA Mode In this mode, separate receive (RX) and transmit (TX) DMA channels move data between the UART and memory. The software does not have to move data, it just has to set up the appropriate transfers either through the descriptor mechanism or through autobuffer mode.
Page 816: Mixing Modes
Programming Model If another DMA is started while data is still pending in the UART trans- mitter, there is no need to pulse the bit to initiate the second DMA. ETBEI If, however, the recent byte has already been loaded into the registers (that is, the bit is set), then the...
Page 817: Uart Registers
UART Port Controllers the interrupt occurs, software can write new data into the regis- UARTx_THR ter as soon as the bit permits. If the bit cannot be set, software THRE SYNC can poll the bit instead. DMA_RUN When switching from non-DMA to DMA operation, take care that the very first DMA request is issued properly.
Page 818 UART Registers Table 13-2. UART Register Overview Name Address DLAB Operation Reset Function Offset Value UARTx_RBR 0x0000 0x00 Receive buffer register UARTx_THR 0x0000 0x00 Transmit hold register UARTx_DLL 0x0000 0x01 Divisor latch low byte UARTx_IER 0x0004 0x00 Interrupt enable regis- UARTx_DLH 0x0004 0x00...
Page 819: Uartx_Lcr Registers
UART Port Controllers UARTx_LCR Registers registers, shown in Figure 13-7, control the format of UARTx_LCR received and transmitted character frames. UART Line Control Registers (UARTx_LCR) 15 14 13 12 11 10 Reset = 0x0000 UART0: 0xFFC0 040C UART1: 0xFFC0 200C DLAB (Divisor Latch Access) WLS[1:0] (Word Length Select) 1 - Enables access to UARTx_DLL...
Page 820 UART Registers bit inserts one additional bit between the most significant data bit and the first stop bit. The polarity of this so-called parity bit depends on data and the control bits. Both transmitter and receiver calcu- late the parity value. The receiver compares the received parity bit with the expected value and issues a parity error if they don’t match.
Page 821: Uartx_Mcr Registers
UART Port Controllers If set, the bit forces the TX pin to low asynchronously, regardless of whether or not data is currently transmitted. It functions even when the UART clock is disabled. Since the TX pin normally drives high, it can be used as a flag output pin, if the UART is not used.
Page 822: Uartx_Lsr Registers
UART Registers UARTx_LSR Registers registers contain UART status information as shown in UARTx_LSR Figure 13-9. UART Line Status Registers (UARTx_LSR) 15 14 13 12 11 10 Reset = 0x0060 UART0: 0xFFC0 0414 UART1: DR (Data Ready) 0xFFC0 2014 0 - No new data 1 - UARTx_RBR holds new data TEMT (TSR and UARTx_THR Empty)
Page 823 UART Port Controllers bit indicates that the received parity bit does not match the expected value. The bit is set simultaneously with the bit. The cleared when the register is read. Invalid parity bits can be simulated by setting the bit in the register.
Page 824: Uartx_Thr Registers
UART Registers UARTx_THR Registers The write-only registers, shown in Figure 13-10, are mapped to UARTx_THR the same address as the read-only registers. To UARTx_RBR UARTx_DLL access , the bit in must be cleared. When the UARTx_THR DLAB UARTx_LCR bit is cleared, writes to this address target the register, and DLAB UARTx_THR...
Page 825: Uartx_Ier Registers
UART Port Controllers UARTx_IER Registers registers, shown in Figure 13-12, are used to enable UARTx_IER requests for system handling of empty or full states of UART data regis- ters. Unless polling is used as a means of action, the and/or ERBFI ETBEI bits in this register are normally set.
Page 826 UART Registers UART Interrupt Enable Registers (UARTx_IER) 15 14 13 12 11 10 Reset = 0x0000 UART0: 0xFFC0 0404 UART1: ERBFI (Enable Receive 0xFFC0 2004 Buffer Full Interrupt) 0 - No interrupt ELSI (Enable RX Status Interrupt) 1 - Generate RX interrupt if 0 - No interrupt DR bit in UARTx_LSR is 1 - Generate line status interrupt if...
Page 827: Uartx_Iir Registers
UART Port Controllers UARTx_IIR Registers When cleared, the bit signals that an interrupt is pending. The NINT STA- field indicates the highest priority pending interrupt. The receive line status has the highest priority; the empty interrupt has the low- UARTx_THR est priority.
Page 828: Uartx_Dll And Uartx_Dlh Registers
UART Registers Because of the destructive nature of these read operations, special care should be taken. For more information, see the Memory chap- ter of the ADSP-BF53x/BF56x Blackfin Processor Programming Reference. UARTx_DLL and UARTx_DLH Registers registers are mapped to the same addresses as the UARTx registers.
Page 829: Uartx_Scr Registers
UART Port Controllers UARTx_SCR Registers The contents of the 8-bit registers, shown in Figure 13-15, are UARTx_SCR reset to 0x00. They are used for general-purpose data storage and do not control the UART hardware in any way. UART Scratch Registers (UARTx_SCR) 15 14 13 12 11 10 Reset = 0x0000 UART0:...
Page 830: Programming Examples
Programming Examples bit enables the UART clocks. It also resets the state machine and UCEN control registers when cleared. Note that the bit was not present in previous UART implementa- UCEN tions. It has been introduced to save power if the UART is not used. When porting code, be sure to enable this bit.
Page 831 UART Port Controllers w[p0+UART0_DLL-UART0_GCTL] = r0; /* write lower byte to DLL r7 = r0 >> 8; w[p0+UART0_DLH-UART0_GCTL] = r7; /* write upper byte to DLH r7 = STB | WLS(8) (z); /* clear DLAB again and con- fig to */ w[p0+UART0_LCR-UART0_GCTL] = r7;...
Page 832 Programming Examples r7 = r7 - r5; r7 >>= 4; /* r7 holds the 'x' of TIMERx_CONFIG now */ r5 = TIMEN0 (z); r5 <<= r7; /* r5 holds TIMENx/TIMDISx now */ r6 = TRUN0 | TOVL_ERR0 | TIMIL0 (z); r6 <<= r7;...
Page 833 UART Port Controllers r7 = OUT_DIS | IRQ_ENA | PERIOD_CNT | PWM_OUT (z); w[p1 + TIMER0_CONFIG - TIMER0_CONFIG] = r7; w[p5 + TIMER_ENABLE - TIMER_STATUS] = r5; uart_autobaud.delay: r7 = w[p5 + TIMER_STATUS - TIMER_STATUS] (z); r7 = r7 & r5; CC = r7 == 0;...
Page 834 Programming Examples The subroutine in Listing 13-4 transmits a character by polling operation. Listing 13-4. UART Character Transmission /******************************************************* Transmit a single byte by polling the THRE bit. Input parameters: r0 holds the character to be transmitted p0 contains UARTx_GCTL register address Return values: none *******************************************************/ uart_putc:...
Page 835 UART Port Controllers [--sp] = rets; [--sp] = r0; uart_puts.loop: r0 = b[p1++] (z); CC = r0 == 0; if CC jump uart_puts.exit; call uart_putc; jump uart_puts.loop; uart_puts.exit: r0 = [sp++]; rets = [sp++]; rts; uart_puts.end: Note that polling the register for transmit purposes may clear UART0_LSR the receive error latch bits.
Page 836 Programming Examples r5 = b[p2++] (z); /* load next byte */ w[p0+UART0_THR-UART0_GCTL] = r5; jump uart_loop; uart_loop.error: jump uart_loop; In non-DMA interrupt operation, the three UART interrupt request lines may or may not be ORed together in the SIC controller. If they had three different service routines, they may look as shown in Listing 13-7.
Page 837 UART Port Controllers isr_uart_tx.final: r7 = w[p0+UART0_IER-UART0_GCTL] (z); /* clear TX interrupt enable */ bitclr(r7, bitpos(ETBEI)); /* ensure this sequence is not */ w[p0+UART0_IER-UART0_GCTL] = r7; /* interrupted by other IER accesses */ ssync; r7 = [sp++]; astat = [sp++]; rti;...
Page 838 Programming Examples p1.l = lo(IMASK); p1.h = hi(IMASK); r0.l = lo(isr_uart_tx); /* register service routine */ r0.h = hi(isr_uart_tx); /* UART0 TX defaults to IVG10 */ r0 = [p1 + IMASK - IMASK]; /* unmask interrupt in CEC */ bitset(r0, bitpos(EVT_IVG10)); [p1] = r0;...
Page 839 UART Port Controllers wait4dma: /* just one way to synchronize with the service routine r0 = w[p5+DMA9_IRQ_STATUS-DMA9_CONFIG] (z); CC = bittst(r0,bitpos(DMA_RUN)); if CC jump wait4dma; p1.l=lo(sWorld); p1.h=hi(sWorld); call uart_puts; forever: jump forever; isr_uart_tx: [--sp] = astat; [--sp] = r7; r7 = DMA_DONE (z); /* W1C interrupt request */ w[p5+DMA9_IRQ_STATUS-DMA9_CONFIG] = r7;...
Page 840 Programming Examples 13-42 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 841: Overview
14 GENERAL-PURPOSE PORTS This chapter describes the general-purpose ports. Following an overview and a list of key features is a block diagram of the interface and a descrip- tion of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview The ADSP-BF534, ADSP-BF536, and ADSP-BF537 Blackfin processors feature a rich set of peripherals, which through a powerful pin multiplex-...
Page 842: Features
Features Table 14-1. General-Purpose and Special Function Signals (Cont’d) Peripheral Signals SPORTs Data (8), clock (4), frame sync (4) UARTs Data (4) Timers PWM/capture/clock (8), alternate clock input (8), alternate cap- ture input (3) General-Purpose I/O GPIO (48) Handshake MemDMA MemDMA request (2) 1 ADSP-BF536 and ADSP-BF537 only.
Page 843: Interface Overview
General-Purpose Ports Port H provides 16 pins: • MII/RMII signals (ADSP-BF536 and ADSP-BF537 only) • GPIOs Port J provides 12 pins: • SPORT0 signals • TWI signals • CAN signals • Some alternate timer inputs • Additional SPI slave select signals •...
Page 844: External Interface
Interface Overview registers ( , and ). The competing periph- PORTF_FER PORTG_FER PORTH_FER erals on port F, port G, and port H are controlled by the multiplexer control register ( PORT_MUX In this chapter, the naming convention for registers and bits uses a lower case to represent F, G, or H.
Page 845: Port G Structure
General-Purpose Ports This allows for unique applications like autobaud detection. Similarly, timer 6 can be used to capture UART1 RX through TACI6 PFTE cleared. If the bit is set, timer 6 can still capture the same pin PFTE through the regular input.
Page 846: Port H Structure
Interface Overview SPORT1 signals are multiplexed with PPI data signals . Thus, PPID15–8 with an 8-bit PPI configuration, no restrictions apply to SPORT1. With a 10-bit PPI configuration, the secondary SPORT1 data signals are not available. However, in a 12-bit PPI configuration, only the SPORT1 transmit channel remains functional.
Page 847: Port J Structure
General-Purpose Ports Port H provides most of the signals of the ADSP-BF536 and ADSP-BF537 MII or alternate RMII interface. Refer to Chapter 8, “Ethernet MAC”, for information about how to configure MII versus RMII mode. The three alternate timer capture inputs are not gated by the function enable or multiplexer control registers.
Page 848: Internal Interfaces
Interface Overview Port J does not provide GPIO functionality. The CAN pins share func- tionality with the secondary SPORT0 data pins, as well as with SPI slave select SSEL7. With the CAN port active, the SPORT0 can still be used in 6-pin mode.
Page 849: Performance/Throughput
General-Purpose Ports register controls the muxing schemes of port F, port G and PORT_MUX port J. The function enable register ( ) enables PORTF_FER PORTG_FER PORTH_FER the peripheral functionality for each individual pin of port x. Performance/Throughput , and pins are synchronized to the system clock ( SCLK When configured as outputs, the GPIOs can transition once every system clock cycle.
Page 850: General-Purpose I/O Modules
Description of Operation mode, set the respective direction bit in the register. To PORTxIO_DIR make the pin a digital input or interrupt input, enable its input driver in register. PORTxIO_INEN By default all peripheral pins are configured as inputs after reset. port F, port G, and port H pins are in GPIO mode.
Page 851 General-Purpose Ports The GPIO direction registers are read-write registers with each bit posi- tion corresponding to a particular GPIO. A logic 1 configures a GPIO as an output, driving the state contained in the GPIO data register if the peripheral function is not enabled by the function enable registers. A logic 0 configures a GPIO as an input.
Page 852 Description of Operation Table 14-2. GPIO Value Register Pin Interpretation POLAR EDGE BOTH Effect of MMR Settings Pin that is high reads as 1; pin that is low reads as 0 If rising edge occurred, pin reads as 1; otherwise, pin reads as 0 Pin that is low reads as 1;...
Page 853 General-Purpose Ports 0x0001 to the GPIO set register drives a logic 1 on the pin without affecting the state of any other pins. The GPIO set registers are typi- cally also used to generate GPIO interrupts by software. Read operations from the GPIO set registers return the content of the GPIO data registers.
Page 854: Gpio Interrupt Processing
Description of Operation The state of the GPIOs can be read through any of these data, set, clear, or toggle registers. However, the returned value reflects the state of the input pin only if the proper input enable bit in the register is set.
Page 855 General-Purpose Ports The GPIO interrupt sensitivity registers are used to configure each of the inputs as either a level-sensitive or an edge-sensitive source. When using an edge-sensitive mode, an edge detection circuit is used to prevent a situ- ation where a short event is missed because of the system clock rate. The GPIO interrupt sensitivity register has no effect on GPIOs that are defined as outputs.
Page 856 Description of Operation Interrupt A and interrupt B operate independently. For example, writing 1 to a bit in the mask interrupt A register does not affect interrupt channel B. This facility allows GPIOs to generate GPIO interrupt A, GPIO inter- rupt B, both GPIO interrupts A and B, or neither.
Page 857 General-Purpose Ports START IS THE GPIO ENABLED IN PORTxIO_MASKA_D? (INPUT) IS THE GPIO SET IS THE INPUT AS AN OUTPUT IN DRIVER ENABLED IN PORTxIO_DIR? PORTxIO_INEN? (OUTPUT) IS THE GPIO EDGE-SENSITIVE (LEVEL SENSITIVE) (EDGE SENSITIVE) IS THE GPIO AS DEFINED IN SET TO ONE? PORTxIO_EDGE? IS EDGE...
Page 858 Description of Operation register alters all bits in the register, writes to the mask interrupt clear reg- ister can be used to clear a single bit or a few bits only. No read-modify-write operations are required. The mask interrupt clear registers are write-1-to-clear registers. All ones contained in the value written to the mask interrupt clear register clear the respective bits in the mask interrupt register.
Page 859 General-Purpose Ports Although each GPIO module provides two independent interrupt chan- nels, the interrupt A channels of port F and port G are ORed as shown in Figure 14-6. The total number of GPIO interrupt channels is five, therefore. IRQ27 PORTFIO_MASKA_D IRQ31 PORTFIO_MASKB_D...
Page 860: Programming Model
Programming Model Programming Model Figure 14-7 Figure 14-8 show the programming model for the gen- eral-purpose ports. PERIPHERAL GPIO OR WRITE PORT_MUX, WRITE PORTx_FER PERIPHERAL? TO SET APPROPRIATE PERIPHERAL BITS GPIO SEE PERIPHERAL FOR MORE DETAILS WRITE PORTx_FER TO CLEAR APPROPRIATE PFx, PGx, AND PHx BITS OUTPUT GPIO OUTPUT...
Page 861 General-Purpose Ports EDGE WRITE PORTxIO_EDGE TO SET EDGE OR LEVEL APPROPRIATE BITS FOR EDGE SENSITIVITY SENSITIVE? LEVEL EDGE RISING/ WRITE PORTxIO_EDGE TO CLEAR RISING OR FALLING FALLING OR BOTH? APPROPRIATE BITS FOR LEVEL SENSITIVITY BOTH WRITE PORTxIO_BOTH TO SET HIGH LEVEL HIGH APPROPRIATE BITS FOR BOTH EDGE SENSITIVITY OR LOW?
Page 862: Memory-Mapped Gpio Registers
Memory-Mapped GPIO Registers Memory-Mapped GPIO Registers The GPIO registers are part of the system memory-mapped registers (MMRs). Figure 14-9 through Figure 14-27 on page 14-34 illustrate the GPIO registers. The addresses of the programmable flag MMRs appear in Appendix B. Port Multiplexer Control Register (PORT_MUX) 15 14 13 12 11 10 Reset = 0x0000...
Page 863 General-Purpose Ports Function Enable Registers (PORTx_FER) For all bits, 0 - GPIO mode, 1 - Enable peripheral function 15 14 13 12 11 10 Port F: Reset = 0x0000 0xFFC0 3200 Port G: 0xFFC0 3204 Port H: 0xFFC0 3208 Px15 Px14 Px13 Px12...
Page 864 Memory-Mapped GPIO Registers GPIO Input Enable Registers (PORTxIO_INEN) For all bits, 0 - Input Buffer Disabled, 1 - Input Buffer Enabled 15 14 13 12 11 10 Port F: Reset = 0x0000 0xFFC0 0740 Port G: 0xFFC0 1540 Px0 Input Enable Port H: 0xFFC0 1740 Px1 Input Enable...
Page 865 General-Purpose Ports GPIO Set Registers (PORTxIO_SET) Write-1-to-set 15 14 13 12 11 10 Reset = 0x0000 Port F: 0xFFC0 0708 Port G: 0xFFC0 1508 Set Px0 Port H: Set Px1 0xFFC0 1708 Set Px2 Set Px3 Set Px15 Set Px4 Set Px14 Set Px5 Set Px13...
Page 866 Memory-Mapped GPIO Registers GPIO Toggle Registers (PORTxIO_TOGGLE) Write-1-to-toggle 15 14 13 12 11 10 Reset = 0x0000 Port F: 0xFFC0 070C Port G: 0xFFC0 150C Toggle Px0 Port H: Toggle Px1 0xFFC0 170C Toggle Px2 Toggle Px3 Toggle Px15 Toggle Px4 Toggle Px14 Toggle Px5 Toggle Px13...
Page 867 General-Purpose Ports Interrupt Sensitivity Registers (PORTxIO_EDGE) For all bits, 0 - Level, 1 - Edge 15 14 13 12 11 10 Reset = 0x0000 Port F: 0xFFC0 0738 Port G: 0xFFC0 1538 Px0 Sensitivity Port H: Px1 Sensitivity 0xFFC0 1738 Px2 Sensitivity Px3 Sensitivity Px15 Sensitivity...
Page 868 Memory-Mapped GPIO Registers GPIO Mask Interrupt A Registers (PORTxIO_MASKA) For all bits, 1 - Enable, 0 - Disable 15 14 13 12 11 10 Port F: Reset = 0x0000 0xFFC0 0710 Port G: 0xFFC0 1510 Enable Px0 Interrupt A Port H: 0xFFC0 1710 Enable Px1 Interrupt A Enable Px2 Interrupt A...
Page 869 General-Purpose Ports GPIO Mask Interrupt A Set Registers (PORTxIO_MASKA_SET) For all bits, 1 - Set 15 14 13 12 11 10 Reset = 0x0000 Port F: 0xFFC0 0718 Port G: 0xFFC0 1518 Set Px0 Interrupt A Port H: Enable 0xFFC0 1718 Set Px1 Interrupt A Enable Set Px2 Interrupt A...
Page 870 Memory-Mapped GPIO Registers GPIO Mask Interrupt B Set Registers (PORTxIO_MASKB_SET) For all bits, 1 - Set 15 14 13 12 11 10 Port F: Reset = 0x0000 0xFFC0 0728 Port G: 0xFFC0 1528 Set Px0 Interrupt B Port H: Enable 0xFFC0 1728 Set Px1 Interrupt B Enable...
Page 871 General-Purpose Ports GPIO Mask Interrupt A Clear Registers (PORTxIO_MASKA_CLEAR) For all bits, 1 - Clear 15 14 13 12 11 10 Reset = 0x0000 Port F: 0xFFC0 0714 Port G: 0xFFC0 1514 Clear Px0 Interrupt A Port H: Enable 0xFFC0 1714 Clear Px1 Interrupt A Enable Clear Px2 Interrupt A...
Page 872 Memory-Mapped GPIO Registers GPIO Mask Interrupt B Clear Registers (PORTxIO_MASKB_CLEAR) For all bits, 1 - Clear 15 14 13 12 11 10 Port F: Reset = 0x0000 0xFFC0 0724 Port G: 0xFFC0 1524 Clear Px0 Interrupt B Port H: Enable 0xFFC0 1724 Clear Px1 Interrupt B Enable...
Page 873 General-Purpose Ports GPIO Mask Interrupt A Toggle Registers (PORTxIO_MASKA_TOGGLE) For all bits, 1 - Toggle 15 14 13 12 11 10 Port F: Reset = 0x0000 0xFFC0 071C Port G: 0xFFC0 151C Toggle Px0 Interrupt A Port H: Enable 0xFFC0 171C Toggle Px1 Interrupt A Toggle Px15 Enable...
Page 874: Programming Examples
Programming Examples GPIO Mask Interrupt B Toggle Registers (PORTxIO_MASKB_TOGGLE) For all bits, 1 - Toggle 15 14 13 12 11 10 Port F: Reset = 0x0000 0xFFC0 072C Port G: 0xFFC0 152C Toggle Px0 Interrupt B Port H: Enable 0xFFC0 172C Toggle Px1 Interrupt B Enable Toggle Px15...
Page 875 General-Purpose Ports r0.l = 0x0000; w[p0] = r0; /* set port f direction register to enable some GPIO as output, remaining are input */ p0.l = lo(PORTFIO_DIR); p0.h = hi(PORTFIO_DIR); r0.h = 0x0000; r0.l = 0x0FC0; w[p0] = r0; ssync; /* set port f clear register */ p0.l = lo(PORTFIO_CLEAR);...
Page 876 Programming Examples 14-36 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 877: Overview And Features
15 GENERAL-PURPOSE TIMERS This chapter describes the general-purpose timer module. Following an overview and a list of key features is a description of operation and func- tional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview and Features The processor features one general-purpose timer module that contains eight identical 32-bit timers.
Page 878: Interface Overview
Interface Overview Feature highlights are: • Synchronous operation of all timers • Consistent management of period and pulse width values • Interaction with PPI module for video frame sync operation • Autobaud detection for CAN and both UART modules • Graceful bit pattern termination when stopping •...
Page 879 General-Purpose Timers BLACKFIN SIC CONTROLLER GP TIMERS TIMER_STATUS TIMER_ENABLE TIMER_DISABLE PORT CONTROL Figure 15-1. Timer Block Diagram The timer module features a global infrastructure to control synchronous operation of all timers if required. The internal structure of the individual timers is illustrated by Figure 15-2, which shows the details of timer 0 rep- resentatively.
Page 880: External Interface
Interface Overview TIMER 0 TIMER0_CONFIG LEADING EDGE TIMER0_PERIOD (WRITE) TIMEN0 ENABLE LATCH TIMDIS0 TIMER0_PERIOD (READ) PERIOD TRUN0 MATCH COMPARATOR TOVF_ERR0 INTERRUPT SCLK CONTROL TMRCLK TIMIL0 TIMER0_COUNTER OVERFLOW TACLK0 TMR0 WIDTH MATCH COMPARATOR TMR0 CONTROL TIMER0_WIDTH (READ) EDGE DETECTOR TACI0 TIMER0_WIDTH (WRITE) TRAILING EDGE Figure 15-2.
Page 881 General-Purpose Timers Alternate clock ( ) and capture ( ) inputs are found on port F, TACLKx TACIx port H and port J. The pins can alternatively clock the timers in TACLKx mode. PWM_OUT mode, timer 0, timer 1, and timer 6 feature inputs that WDTH_CAP TACIx...
Page 882: Internal Interface
Description of Operation Clock and capture input pins are sampled every cycle. The duration SCLK of every low or high state must be one minimum. The maximum SCLK allowed frequency of timer input signals is , therefore. SCLK Internal Interface Timer registers are always accessed by the core through the 16-bit PAB bus.
Page 883 General-Purpose Timers software using W1C operations to clear the interrupt request. The global is 32-bits wide. A single atomic 32-bit read can report the TIMER_STATUS status of all eight timers consistently. Before a timer can be enabled, its mode of operation is programmed in the individual timer-specific registers.
Page 884: Interrupt Processing
Description of Operation Interrupt Processing Each of the eight timers can generate a single interrupt. The eight result- ing interrupt signals are routed to the system interrupt controller block for prioritization and masking. The timer status register (TIMER_STATUS) latches the timer interrupts to provide a means for software to determine the interrupt source.
Page 885 General-Purpose Timers bit in the register at the very beginning of the inter- TIMILx TIMER_STATUS rupt service routine to avoid missing any timer events. Figure 15-3 shows the timers interrupt structure. ILLEGAL TIMERX_WIDTH COUNT = WIDTH COUNT = PERIOD ILLEGAL TIMERX_PERIOD TRAILING EDGE...
Page 886: Illegal States
Description of Operation Illegal States Every timer features an error detection circuit. It handles overflow situa- tions but also performs pulse width vs. period plausibility checks. Errors are reported by the bits in the register and the TOVF_ERRx TIMER_STATUS bit field in the individual registers.
Page 887 General-Purpose Timers The following table can be read as: “In mode __ at event __, if is __ and is __, then is __ and TIMERx_PERIOD TIMERx_WIDTH ERR_TYP is __.” TOVF_ERR Startup error conditions do not prevent the timer from starting. Similarly, overflow and rollover error conditions do not stop the timer.
Page 888 Description of Operation Table 15-1. Overview of Illegal States (Cont’d) Mode Event TIMERx_ TIMERx_ ERR_TYP TOVF_ERR PERIOD WIDTH PWM_OUT, Startup Anything == 0 b#01 PERIOD_ This case is not detected at startup, but results in an overflow CNT = 0 error once the counter counts through its entire range.
Page 889: Modes Of Operation
General-Purpose Timers Modes of Operation The following sections provide a functional description of the gen- eral-purpose timers in various operating modes. Pulse Width Modulation (PWM_OUT) Mode Use the mode for PWM signal or single-pulse generation, for PWM_OUT interval timing or for periodic interrupt generation. Figure 15-4 illustrates mode.
Page 890 Modes of Operation DATA BUS TIMERx_PERIOD TIMERx_WIDTH TMRCLK PWM_CLK CLOCK RESET TACLKx TIMERx_COUNTER SCLK TIN_SEL CLK_SEL EQUAL? EQUAL? TIMER_ENABLE ASSERT DEASSERT PULSE_HI PWMOUT TOGGLE_HI LOGIC OUT_DIS INTERRUPT TMRx PERIOD_CNT Figure 15-4. Timer Flow Diagram, PWM_OUT Mode generates a repeating (and possibly modulated) waveform. It generates an interrupt (if enabled) at the end of each period and stops only after it is disabled.
Page 891: Output Pad Disable
General-Purpose Timers Output Pad Disable The output pin can be disabled in mode by setting the PWM_OUT OUT_DIS bit in the timer configuration register. The pin is then three-stated TMRx regardless of the setting of . This can reduce PULSE_HI TOGGLE_HI power consumption when the output signal is not being used.
Page 892: Pulse Width Modulation Waveform Generation
Modes of Operation The pulse width may be programmed to any value from 1 to (2 -1), inclusive. Pulse Width Modulation Waveform Generation If the bit is set, the internally clocked timer generates rectan- PERIOD_CNT gular signals with well-defined period and duty cycle (PWM patterns). This mode also generates periodic interrupts for real-time signal processing.
Page 893 General-Purpose Timers EXAMPLE TIMER ENABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 1) SCLK TIMERx_PERIOD TIMERx_WIDTH TIMERx_COUNTER TIMENx TRUNx TMRx, PULSE_HI = 0 TMRx, PULSE_HI = 1 W1S TO TIMER_ENABLE Figure 15-6. Timer Enable Timing If enabled, a timer interrupt is generated at the end of each period. An interrupt service routine (ISR) must clear the interrupt latch bit ( TIMILx and might alter period and/or width values.
Page 894: Pulse_Hi Toggle Mode
Modes of Operation flags. Pulse width values greater than the period value are TOVL_ERRx not recommended. Similarly, is not a valid operation. TIMERx_WIDTH Duty cycles of 0% are not supported. To generate the maximum frequency on the output pin, set the TMRx period value to 2 and the pulse width to 1.
Page 895 General-Purpose Timers active low and active high pulses, taken together, create two halves of a fully arbitrary rectangular waveform. The effective waveform is still active high when is set and active low when is cleared. The PULSE_HI PULSE_HI value of the bit has no effect unless the mode is TOGGLE_HI PWM_OUT...
Page 896 Modes of Operation WAVEFORM WAVEFORM PERIOD 1 PERIOD 2 TIMER TIMER TIMER TIMER PERIOD 1 PERIOD 2 PERIOD 3 PERIOD 4 TOGGLE_HI = 1 TMR0 PULSE_HI = 1 ACTIVE ACTIVE ACTIVE ACTIVE HIGH HIGH TOGGLE_HI = 1 TMR1 PULSE_HI = 1 ACTIVE ACTIVE ACTIVE...
Page 897 General-Purpose Timers When , software updates the timer period and timer pulse TOGGLE_HI width registers once per waveform period. When , software TOGGLE_HI = 1 updates the timer period and timer pulse width registers twice per wave- form. Period values are half as large. In odd-numbered periods, write ) instead of to the timer pulse width register in Period –...
Page 898: Externally Clocked Pwm_Out
Modes of Operation write(TIMERx_PERIOD, per1) ; write(TIMERx_WIDTH, per1 - wid1) ; waitfor (interrupt) ; write(TIMERx_PERIOD, per2) ; write(TIMERx_WIDTH, wid2) ; As shown in this example, the pulses produced do not need to be symmet- ric ( does not need to equal ).
Page 899: Using Pwm_Out Mode With The Ppi
General-Purpose Timers When is set, the counter resets to 0x0 at startup and increments CLK_SEL on each rising edge of . The pin transitions on rising edges PWM_CLK TMRx . There is no way to select the falling edges of .
Page 900 Modes of Operation read 0 or by waiting for the last interrupt (if enabled). Note the timer can- not be reconfigured ( cannot be written to a new value) TIMERx_CONFIG until after the timer stops and reads 0. TRUNx single pulse mode ( ), it is not necessary to PWM_OUT PERIOD_CNT = 0...
Page 901 General-Purpose Timers EXAMPLE TIMER DISABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 1) SCLK TIMERx_PERIOD TIMERx_WIDTH TIMERx_COUNTER TIMENx TRUNx TMRx, PULSE_HI = 0 TMRx, PULSE_HI = 1 W1C TO TIMER_DISABLE Figure 15-10. Timer Disable Timing If necessary, the processor can force a timer in mode to abort PWM_OUT immediately.
Page 902: Pulse Width Count And Capture (Wdth_Cap) Mode
Modes of Operation Pulse Width Count and Capture (WDTH_CAP) Mode Use the mode, often simply called “capture mode,” to measure WDTH_CAP pulse widths on the input pins, or to “receive” PWM sig- TMRx TACIx nals. Figure 15-11 shows a flow diagram for mode.
Page 903 General-Purpose Timers DATA BUS TIMERx_PERIOD TIMERx_WIDTH SCLK RESET TIMERx_COUNTER PULSE_HI PULSE_HI TMRx TMRx TRAILING LEADING EDGE EDGE DETECT DETECT TIMER_ENABLE TOVF_ERR PERIOD_CNT INTERRUPT LOGIC INTERRUPT Figure 15-11. Timer Flow Diagram, WDTH_CAP Mode mode, these three events always occur at the same time as one WDTH_CAP unit: 1.
Page 904 Modes of Operation bit in the register controls the point in PERIOD_CNT TIMERx_CONFIG time at which this set of transactions is executed. Taken together, these three events are called a measurement report. The bit does not TOVF_ERRx get set at a measurement report. A measurement report occurs at most once per input signal period.
Page 905 General-Purpose Timers SCLK TMRx, PULSE_HI = 0 TMRx, PULSE_HI = 1 TIMERx_COUNTER TIMERx_PERIOD BUFFER TIMERx_WIDTH BUFFER TIMERx_PERIOD TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx STARTS MEASUREMENT MEASUREMENT COUNTING REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 15-12.
Page 906 Modes of Operation SCLK TMRx, PULSE_HI = 0 TMRx, PULSE_HI = 1 TIMERx_COUNTER TIMERx_PERIOD BUFFER TIMERx_WIDTH BUFFER TIMERx_PERIOD TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx STARTS MEASUREMENT MEASUREMENT MEASUREMENT COUNTING REPORT REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN.
Page 907 General-Purpose Timers (because no measurement report occurred to copy the value captured in the width buffer register to ). See the first interrupt in TIMERx_WIDTH Figure 15-14. When using the mode described above to measure PERIOD_CNT the width of a single pulse, it is recommended to disable the timer after taking the interrupt that ends the measurement interval.
Page 908 Modes of Operation SCLK TMRx, PULSE_HI = 0 TMRx, PULSE_HI = 1 TIMERx_COUNTER 0xFFFF 0xFFFF 0xFFFF 0xFFFF FFFC FFFD FFFE FFFF TIMERx_PERIOD BUFFER TIMERx_WIDTH BUFFER TIMERx_PERIOD TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx STARTS ERROR MEASUREMENT COUNTING REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN.
Page 909 General-Purpose Timers SCLK TMRx, PULSE_HI = TMRx, PULSE_HI = TIMERx_COUNTER 0xFFFF 0xFFFF 0xFFFF 0xFFFF FFFC FFFD FFFE FFFF TIMERx_PERIOD BUFFER TIMERx_WIDTH BUFFER TIMERx_PERIOD TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx STARTS MEASUREMENT ERROR COUNTING REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN.
Page 910: Autobaud Mode
Modes of Operation overflowed and , the PERIOD_CNT = 0 TIMERx_PERIOD TIMERx_WIDTH registers were updated only if a trailing edge was detected at a previous measurement report. Software can count the number of error report interrupts between mea- surement report interrupts to measure input signal periods longer than 0xFFFF FFFF.
Page 911 General-Purpose Timers The timer works as a counter clocked by an external source, which can also be asynchronous to the system clock. The current count in represents the number of leading edge events detected. TIMERx_COUNTER Setting the field to b#11 in the register enables this TMODE TIMERx_CONFIG...
Page 912: Programming Model
Programming Model subsequent leading edge increments the count register. After reaching the period value, the bit is set, and an interrupt is generated. The next TIMILx leading edge reloads the timer counter register again with 0x1. The timer continues counting until it is disabled. The bit determines PULSE_HI whether the leading edge is rising (...
Page 913: Timer Registers
General-Purpose Timers If in mode the PWM patterns of the second period differ from PWM_OUT the patterns of the first one, the initialization sequence above might become: 1. Set timer mode to PWM_OUT. 2. Write first value pair. TIMERx_WIDTH TIMERx_PERIOD 3.
Page 914: Timer_Enable Register
Timer Registers Additionally, three registers are shared between the eight timers: • – timer enable register TIMER_ENABLE[15:0] • – timer disable register TIMER_DISABLE[15:0] • – timer status register TIMER_STATUS[31:0] The size of accesses is enforced. A 32-bit access to a timer configuration register or a 16-bit access to a timer pulse width, timer period, or timer counter register results in a Memory-Mapped Register (MMR) error.
Page 915: Timer_Disable Register
General-Purpose Timers Timer Enable Register (TIMER_ENABLE) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 0680 TIMEN7 (Timer7 Enable) TIMEN0 (Timer0 Enable) 1 - Enable timer 1 - Enable timer Read as 1 when enabled Read as 1 when enabled TIMEN6 (Timer6 Enable) TIMEN1 (Timer1 Enable) 1 - Enable timer...
Page 916: Timer_Status Register
Timer Registers Timer Disable Register (TIMER_DISABLE) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 0684 TIMDIS7 (Timer7 Disable) TIMDIS0 (Timer0 Disable) 1 - Disable timer 1 - Disable timer Read as 1 if this timer is enabled Read as 1 if this timer is enabled TIMDIS6 (Timer6 Disable) TIMDIS1 (Timer1 Disable) 1 - Disable timer...
Page 917 General-Purpose Timers which they do when a mode timer stops at the end of a period. PWM_OUT During a register read access, all reserved or unused bits TIMER_STATUS return a 0. For detailed behavior and usage of the bit see “Stopping the Timer TRUNx in PWM_OUT Mode”...
Page 918 Timer Registers Timer Status Register (TIMER_STATUS) All bits are W1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0688 Reset = 0x0000 0000 TRUN7 (Timer7 Slave Enable Status) TIMIL4 (Timer4 Interrupt) Read as 1 if timer Indicates an interrupt request running, W1C to abort in...
Page 919: Timerx_Config Registers
General-Purpose Timers TIMERx_CONFIG Registers The operating mode for each timer is specified by its regis- TIMERx_CONFIG ter. The register, shown in Figure 15-20, may be written TIMERx_CONFIG only when the timer is not running. After disabling the timer in PWM_OUT mode, make sure the timer has stopped running by checking its TRUNx before attempting to reprogram...
Page 920 Timer Registers Timer Configuration Registers (TIMERx_CONFIG) 15 14 13 12 11 10 Reset = 0x0000 For Memory- mapped addresses, see TMODE[1:0] (Timer Mode) Table 15-2. 00 - Reset state - unused 01 - PWM_OUT mode 10 - WDTH_CAP mode 11 - EXT_CLK mode ERR_TYP[1:0] (Error PULSE_HI Type) - RO...
Page 921: Timerx_Counter Registers
General-Purpose Timers Table 15-2. Timer Configuration Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address TIMER4_CONFIG 0xFFC0 0640 TIMER5_CONFIG 0xFFC0 0650 TIMER6_CONFIG 0xFFC0 0660 TIMER7_CONFIG 0xFFC0 0670 TIMERx_COUNTER Registers These read-only registers retain their state when disabled. When enabled, register is reinitialized by hardware based on configu- TIMERx_COUNTER ration and mode.
Page 922: Timerx_Period And Timerx_Width Registers
Timer Registers Timer Counter Registers (TIMERx_COUNTER) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0001 For Memory- mapped addresses, see Table 15-3. Timer Counter[31:16] 15 14 13 12 11 10 Timer Counter[15:0] Figure 15-21.
Page 923 General-Purpose Timers Usage of the register, shown in Figure 15-22, and the TIMERx_PERIOD register, shown in Figure 15-23, varies depending on the TIMERx_WIDTH mode of the timer: • In pulse width modulation mode ( ), both the timer period PWM_OUT and timer pulse width register values can be updated “on-the-fly”...
Page 924 Timer Registers the values for the timer period and/or timer pulse width registers in order to use a different setting for each of the first three timer periods after the timer is enabled, the procedure to follow is: 1. Program the first set of register values. 2.
Page 925 General-Purpose Timers Table 15-4. Timer Period Register Memory-mapped Addresses Register Name Memory-mapped Address TIMER0_PERIOD 0xFFC0 0608 TIMER1_PERIOD 0xFFC0 0618 TIMER2_PERIOD 0xFFC0 0628 TIMER3_PERIOD 0xFFC0 0638 TIMER4_PERIOD 0xFFC0 0648 TIMER5_PERIOD 0xFFC0 0658 TIMER6_PERIOD 0xFFC0 0668 TIMER7_PERIOD 0xFFC0 0678 Timer Width Registers (TIMERx_WIDTH) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 For Memory-...
Page 926: Summary
Timer Registers Table 15-5. Timer Width Register Memory-mapped Addresses (Cont’d) Register Name Memory-mapped Address TIMER4_WIDTH 0xFFC0 064C TIMER5_WIDTH 0xFFC0 065C TIMER6_WIDTH 0xFFC0 066C TIMER7_WIDTH 0xFFC0 067C Summary Table 15-6 summarizes control bit and register usage in each timer mode. Table 15-6. Control Bit and Register Usage Chart Bit / Register PWM_OUT Mode WDTH_CAP Mode...
Page 927 General-Purpose Timers Table 15-6. Control Bit and Register Usage Chart (Cont’d) Bit / Register PWM_OUT Mode WDTH_CAP Mode EXT_CLK Mode TIN_SEL Depends on 1 - Select TACI input Unused CLK_SEL: 0 - Select TMRx input If CLK_SEL = 1, 1 - Count TMRCLK clocks 0 - Count TACLKx clocks...
Page 928: Programming Examples
Programming Examples Table 15-6. Control Bit and Register Usage Chart (Cont’d) Bit / Register PWM_OUT Mode WDTH_CAP Mode EXT_CLK Mode Counter RO: Counts up on RO: Counts up on RO: Counts up on SCLK or PWM_CLK SCLK TMRx event TRUNx Read: Timer slave Read: Timer slave Read: Timer slave...
Page 929 General-Purpose Timers p5.h = hi(PORTF_FER); p5.l = lo(PORTF_FER); r7.l = PF2|PF3|PF4|PF5|PF6|PF7|PF8|PF9; w[p5] = r7; p5.l = lo(PORT_MUX); r7.l = PFTE; w[p5] = r7; (r7:7, p5:5) = [sp++]; rts; timer_port_setup.end: Listing 15-2 generates signals on the ) and ) outputs. TMR4 TMR5 By default, timer 5 generates a continuous PWM signal with a duty cycle of 50% (period = 0x40 SCLKs, width = 0x20 SCLKs) while the PWM sig-...
Page 930 Programming Examples #endif w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; w[p5 + TIMER4_CONFIG - TIMER_ENABLE] = r7; r7 = 0x10 (z); [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r7; r7 = 0x20 (z); [p5 + TIMER4_WIDTH - TIMER_ENABLE] = r7; #ifndef SINGLE_PULSE r7 = 0x40 (z);...
Page 931 General-Purpose Timers bitset(r7, bitpos(EVT_IVG7)); [p5] = r7; p5.h = hi(SIC_IMASK); p5.l = lo(SIC_IMASK); /* assign timer 5 IRQ = IRQ24 to IVG7 */ r7 = -1 (x); [p5 + SIC_IAR0 - SIC_IMASK] = r7; [p5 + SIC_IAR1 - SIC_IMASK] = r7; [p5 + SIC_IAR2 - SIC_IMASK] = r7;...
Page 932 Programming Examples p5.l = lo(TIMER_ENABLE); #ifdef SINGLE_PULSE r7.l = EMU_RUN | IRQ_ENA | OUT_DIS | PWM_OUT; #else r7.l = EMU_RUN | IRQ_ENA | PERIOD_CNT | OUT_DIS | PWM_OUT; #endif w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; r7 = 0x1000 (z); #ifndef SINGLE_PULSE [p5 + TIMER5_PERIOD - TIMER_ENABLE] = r7;...
Page 933 General-Purpose Timers Listing 15-5 illustrates how two timers can generate two non-overlapping clock pulses as typically required for break-before-make scenarios. Both timers are running in mode with = 1 and PWM_OUT PERIOD_CNT = 1. PULSE_HI Figure 15-24 explains how the signal waveform represented by the period P and the pulse width W translates to timer period and width values.
Page 934 Programming Examples Since hardware only updates the written period and width values at the end of periods, software can write new values immediately after the timers have been enabled. Note that both timers’ period expires at exactly the same times with the exception of the first timer 5 interrupt (at IRQ1 which is not visible to timer 4.
Page 935 General-Purpose Timers /* start timers */ r7.l = TIMEN5 | TIMEN4 ; w[p5 + TIMER_ENABLE - TIMER_ENABLE] = r7; /* write values for second period */ [p5 + TIMER4_PERIOD - TIMER_ENABLE] = r3; [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r2; /* r0 functions as signal period counter */ r0.h = hi(N * 2 - 1);...
Page 936 Programming Examples r5.l = 0; r7.l = TIMDIS5 | TIMDIS4; if !CC r7 = r5; w[p5 + TIMER_DISABLE - TIMER_ENABLE] = r7; (r7:5, p5:5) = [sp++]; astat = [sp++]; rti; isr_timer5.end: Listing 15-5 generates N pulses on both timer output pins. Disabling the timers does not corrupt the generated pulse pattern anyhow.
Page 937 General-Purpose Timers r7.l = EMU_RUN|IRQ_ENA|PERIOD_CNT|PULSE_HI|WDTH_CAP; w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; r7.l = TIMEN5; w[p5 + TIMER_ENABLE - TIMER_ ENABLE] = r7; (r7:7, p5:5) = [sp++]; rts; timer5_capture.end: isr_timer5: [--sp] = astat; [--sp] = (r7:7, p5:5); /* clear interrupt request first */ p5.h = hi(TIMER_STATUS);...
Page 938 Programming Examples 15-62 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 939: Overview And Features
16 CORE TIMER This brief chapter describes the core timer. Following an overview, func- tional description, and consolidated register definitions, the chapter concludes with a programming example. Overview and Features The core timer is a programmable 32-bit interval timer which can gener- ate periodic interrupts.
Page 940: External Interfaces
Description of Operation CORE REGISTER ACCESS BUS (RAB) TPERIOD TSCALE TCNTL COUNT REGISTER LOAD LOGIC TIMER INTERRUPT TIMER ENABLE CCLK ZERO AND PRESCALE TCOUNT LOGIC Figure 16-1. Core Timer Block Diagram External Interfaces The core timer does not directly interact with any pins of the chip. Internal Interfaces The core timer is accessed through the 32-bit Register Access Bus (RAB).
Page 941: Interrupt Processing
Core Timer When the timer is enabled by setting the bit in the core timer con- TMREN trol register ( ), the register is decremented once every time TCNTL TCOUNT the prescaler expires, that is, every + 1 number of TSCALE TSCALE CCLK...
Page 942: Core Timer Registers
Core Timer Registers Core Timer Registers The core timer includes four core Memory-Mapped Registers (MMRs), the timer control register ( ), the timer count register ( ), the TCNTL TCOUNT timer period register ( ), and the timer scale register ( ).
Page 943: Tcount Register
Core Timer TCOUNT Register The core timer count register ( , shown in Figure 16-3) decrements TCOUNT once every + 1 clock cycles. When the value of reaches 0, TSCALE TCOUNT an interrupt is generated and the bit of the register is set.
Page 944: Tperiod Register
Core Timer Registers TPERIOD Register When auto-reload is enabled, the register is reloaded with the TCOUNT value of the core timer period register ( , shown in Figure 16-4), TPERIOD whenever reaches 0. Writes to are ignored when the timer TCOUNT TPERIOD is running.
Page 945: Tscale Register
Core Timer TSCALE Register The core timer scale register ( , shown in Figure 16-5,) stores the TSCALE scaling value that is one less than the number of cycles between decre- ments of . For example, if the value in the register is 0, the TCOUNT TSCALE...
Page 946 Programming Examples r0.l = lo(isr_core_timer); r0.h = hi(isr_core_timer); [p1 + EVT6 - IMASK] = r0; r0 = [p1]; bitset(r0, bitpos(EVT_IVTMR)); [p1] = r0; /* Prescaler = 50, Period = 10,000,000, First Period = 20,000,000 p1.l = lo(TCNTL); p1.h = hi(TCNTL); r0 = 50 (z);...
Page 947: Overview And Features
17 WATCHDOG TIMER This brief chapter describes the watchdog timer. Following an overview, functional description, and consolidated register definitions, the chapter concludes with programming examples. Overview and Features The processor includes a 32-bit timer that can be used to implement a software watchdog function.
Page 948: Interface Overview
Interface Overview Especially in slave boot configurations, a processor reset cannot automati- cally force the part to be rebooted. In this case, the processor may reset without booting again and may negotiate with the host device by the time program execution starts. Alternatively, a watchdog event can cause an NMI event.
Page 949: External Interface
Watchdog Timer External Interface The watchdog timer does not directly interact with any pins of the chip. Internal Interface The watchdog timer is clocked by the system clock . Its registers are SCLK accessed through the 16-bit peripheral access bus PAB. The 32-bit regis- ters must always be accessed by 32-bit read/write WDOG_CNT...
Page 950 Description of Operation To start the watchdog timer: 1. Set the count value for the watchdog timer by writing the count value into the watchdog count register ( ). Since the WDOG_CNT watchdog timer is not enabled yet, the write to the regis- WDOG_CNT ters automatically pre-loads the...
Page 951: Register Definitions
Watchdog Timer If the watchdog is enabled with a zero value loaded to the counter and the bit was cleared, the bit of the watchdog control register is set WDRO WDRO immediately and the counter remains at zero without further decrements. If, however, the bit was set by the time the watchdog is enabled, the WDRO...
Page 952: Wdog_Stat Register
Register Definitions Watchdog Count Register (WDOG_CNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xFFC0 0204 Watchdog Count[31:16] 15 14 13 12 11 10 Watchdog Count[15:0] Figure 17-2. Watchdog Count Register WDOG_STAT Register The 32-bit watchdog status register ( , shown in...
Page 953: Wdog_Ctl Register
Watchdog Timer register is a 32-bit unsigned system memory-mapped regis- WDOG_STAT ter that must be accessed with 32-bit reads and writes. Watchdog Status Register (WDOG_STAT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0208 Reset = 0x0000 0000 Watchdog Status[31:16]...
Page 954 Register Definitions Software can determine whether the watchdog has expired by interrogat- ing the watchdog rolled over ( ) status bit of the watchdog control WDRO register. This is a sticky bit that is set whenever the watchdog timer count reaches 0.
Page 955: Programming Examples
Watchdog Timer Programming Examples Listing 17-1 shows how to configure the watchdog timer so that it resets the chip when it expires. At startup, the code evaluates whether the recent reset event has been caused by the watchdog. Additionally, the example sets the bit to prevent the memory from being rebooted.
Page 956 Programming Examples /* start watchdog timer, reset if expires */ p0.h = hi(WDOG_CNT); p0.l = lo(WDOG_CNT); r0.h = hi(WDOGPERIOD); r0.l = lo(WDOGPERIOD); [p0] = r0; p0.l = lo(WDOG_CTL); r0.l = WDEN | WDEV_RESET; w[p0] = r0; jump _main; _reset.end: The subroutine shown in Listing 17-2 can be called by software to service the watchdog.
Page 957 Watchdog Timer Listing 17-3 is an interrupt service routine that restarts the watchdog. Note that the watchdog must be disabled first. Listing 17-3. Watchdog Restarted by Interrupt Service Routine isr_watchdog: [--sp] = astat; [--sp] = (p5:5, r7:7); p5.h = hi(WDOG_CTL); p5.l = lo(WDOG_CTL);...
Page 958 Programming Examples 17-12 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 959: Overview
18 REAL-TIME CLOCK This chapter describes the Real-Time Clock (RTC). Following an over- view and list of key features is a description of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview The RTC provides a set of digital watch features to the processor, includ- ing time of day, alarm, and stopwatch countdown.
Page 960: Interface Overview
Interface Overview • 24-hour counter • 32768-day counter The RTC increments the 60-second counter once per second and incre- ments the other three counters when appropriate. The 32768-day counter is incremented each day at midnight (0 hours, 0 minutes, 0 seconds). Interrupts can be issued periodically, either every second, every minute, every hour, or every day.
Page 961: Description Of Operation
Real-Time Clock The RTC has dedicated power supply pins that power the clock functions at all times, including when the core power supply is turned off. Figure 18-1 provides a block diagram of the RTC. RTC_PREN 24 HOURS HOURS MINUTES SECONDS EVENT EVENT...
Page 962: Rtc Clock Requirements
Description of Operation RTC Clock Requirements The RTC timer is clocked by a 32.768 kHz crystal external to the proces- sor. The RTC system memory-mapped registers (MMRs) are clocked by this crystal. When the prescaler is disabled, the RTC MMRs are clocked at the 32.768 kHz crystal frequency.
Page 963 Real-Time Clock Write and then wait for the write complete event before pro- RTC_PREN gramming the other registers. It is safe to write to 1 every time RTC_PREN the processor boots. The first time sets the bit, and subsequent writes have no effect, as no state is changed.
Page 964: Rtc Programming Model
RTC Programming Model RTC Programming Model The RTC programming model consists of a set of system MMRs. Soft- ware can configure the RTC and can determine the status of the RTC through reads and writes to these registers. The RTC interrupt control register ( ) and the RTC interrupt status register ( ) pro-...
Page 965: Register Writes
Real-Time Clock 1 Hz TICK POWERED BY RTC V CLOCKED BY 1 Hz TICK POWERED BY INTERNAL V CLOCKED BY SCLK REG WRITE REG READ RTC_ISTAT HOLDING SHADOW 16/32 16/32 REG WRITE MMR WRITE PENDING TO REG WRITE PENDING STATUS WRITE FALLING COMPLETE...
Page 966: Write Latency
RTC Programming Model interrupt. Software does not have to wait for writes to one RTC MMR to complete before writing to another RTC MMR. The write pending status bit is set if any writes are in progress, and the write complete flag is set only when all writes are complete.
Page 967: Register Reads
Real-Time Clock technique is to only post writes to RTC_STAT RTC_ALARM RTC_SWCNT , or immediately after a seconds interrupt or event. All RTC_ICTL RTC_PREN five registers may be written in the same second. W1C bits in the register take effect immediately. RTC_ISTAT Register Reads There is no latency when reading RTC MMRs, as the values come from...
Page 968: Event Flags
RTC Programming Model When the system wakes up from deep sleep state, software does not need to W1C the bits in . All W1C bits are already cleared by hard- RTC_ISTAT ware. The seconds event flag is set when the RTC internal V logic has completed its restart sequence.
Page 969 Real-Time Clock complete and write pending status flags or interrupts to validate the value before using this flag value or enabling the RTC_STAT interrupt. • Hours event flag Valid only after the minute field in is valid. Use the write RTC_STAT complete and write pending status flags or interrupts to validate the value before using this flag value or enabling the...
Page 970: Setting Time Of Day
RTC Programming Model Writes posted together at the beginning of the same second take effect together at the next 1 Hz tick. The following sequence is safe and does not result in any spurious interrupts from a previous state. 1. Wait for 1 Hz tick. 2.
Page 971: Using The Stopwatch
Real-Time Clock 3. Write to current time, 13:10:59. RTC_STAT 4. Read , still get old time 10:45:30. RTC_STAT 5. Wait for 1 Hz tick. 6. Read , get new current time, 13:11:00. RTC_STAT Using the Stopwatch The RTC stopwatch count register ( ) contains the countdown RTC_SWCNT value for the stopwatch.
Page 972: Interrupts
RTC Programming Model Interrupts The RTC can provide interrupts at several programmable intervals: • Per second, minute, hour, and day—based on increments to the respective counters in RTC_STAT • On countdown from a programmable value—value in RTC_SWCNT transitions to 0 or is written with 0 by software (whether it was pre- viously running or already stopped with a count of 0) •...
Page 973 Real-Time Clock interrupts are needed immediately after reset, it is recommended to write so that later read-modify-write accesses function as RTC_ICTL 0x0000 intended. Interrupt status can be determined by reading the RTC interrupt status register ( ). All bits in are sticky.
Page 974: State Transitions Summary
RTC Programming Model DAY, 24 HOURS, HOURS, MINUTES, SECONDS, ALARM, STOPWATCH EVENTS WAKE RTC_ICTL FROM POWER VOLTAGE REGULATOR 1 Hz TICK POWERED BY POWERED BY RTC V EXTERNAL V POWERED BY WRITE INTERNAL V COMPLETE EVENT WAKE FROM DEEP SLEEP ICTL READ RTC_ISTAT SHADOW...
Page 975 Real-Time Clock Table 18-1. Effect of States on RTC MMRs System RTC_ICTL RTC_ISTAT RTC_STAT RTC_ALARM State RTC_SWCNT RTC_PREN power Reset As written Counting As written Full on As written Events Counting As written Sleep As written Events Counting As written Active As written Events...
Page 976 RTC Programming Model Table 18-2. RTC System State Transition Events (Cont’d) At This Event: Execute This Sequence: Wake from deep sleep Wait for seconds event flag to set. Write RTC_ISTAT to acknowledge RTC deep sleep wakeup. Read RTC MMRs as required. The PLL state is now active.
Page 977: Register Definitions
Real-Time Clock Register Definitions The following sections contain the register definitions. Figure 18-4 through Figure 18-9 on page 18-22 illustrate the registers. Table 18-3 shows the functions of the RTC registers. Table 18-3. RTC Register Mapping Register Name Function Notes RTC_STAT RTC status register Holds time of day...
Page 978: Rtc_Stat Register
Register Definitions RTC_STAT Register RTC Status Register (RTC_STAT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined 0xFFC0 0300 Hours[4] (0-23) Day Counter[14:0] (0-32767) 15 14 13 12 11 10 Seconds[5:0] (0-59) Minutes[5:0]...
Page 979: Rtc_Istat Register
Real-Time Clock RTC_ISTAT Register RTC Interrupt Status Register (RTC_ISTAT) All bits are write-1-to-clear, except bit 14 15 14 13 12 11 10 0xFFC0 0308 Reset = 0x0000 Write Complete Stopwatch Event Flag 0 - Writes (if any) not yet 0 - No event complete 1 - Event occurred 1 - All pending writes...
Page 980: Rtc_Alarm Register
Register Definitions RTC_ALARM Register RTC Alarm Register (RTC_ALARM) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 0310 Reset = Undefined Hours[4] (0 to 23) Day[14:0] (0 to 32767) 15 14 13 12 11 10 Seconds[5:0] (0 to 59) Minutes[5:0]...
Page 981: Programming Examples
Real-Time Clock Programming Examples The following RTC code examples show how to enable the RTC pres- caler, how to set up a stopwatch event to take the RTC out of deep sleep mode, and how to use the RTC alarm to exit hibernate state. Each of these code examples assumes that the appropriate header file is included in the source code (that is, for ADSP-BF537 projects).
Page 982: Rtc Stopwatch For Exiting Deep Sleep Mode
Programming Examples RTC Stopwatch For Exiting Deep Sleep Mode Listing 18-2 sets up the RTC to utilize the stopwatch feature to come out of deep sleep mode. This code assumes that the is prop- _RTC_Interrupt erly registered as the ISR for the real-time clock event, the RTC interrupt is enabled in both , and that the RTC prescaler has IMASK...
Page 983 Real-Time Clock P0.L = LO(RTC_SWCNT); R1 = 0x0010(Z); /* set stop-watch to 16 seconds W[P0] = R1.L; /* will produce ~15 second delay */ P0.L = LO(RTC_ICTL); R1 = STOPWATCH(Z); W[P0] = R1.L; /* enable Stop-Watch interrupt */ P0.L = LO(RTC_ISTAT); R1 = 0x807F(Z);...
Page 984: Rtc Alarm To Come Out Of Hibernate State
Programming Examples RTC Alarm to Come Out of Hibernate State Listing 18-3 sets up the RTC to utilize the alarm feature to come out of hibernate state. This code assumes that the prescaler has already been properly enabled. Listing 18-3. Setting RTC Alarm to Exit Hibernate State Hibernate_Code: P0.H = HI(RTC_ALARM);...
Page 985 Real-Time Clock P0.H = HI(VR_CTL); P0.L = LO(VR_CTL); R0 = W[P0](Z); BITCLR(R0, 0); /* Clear FREQ (bits 0 and 1) to */ BITCLR(R0, 1); /* go to Hibernate State BITSET(R0, BITPOS(WAKE)); /* Enable RTC Wakeup W[P0] = R0.L; CLI R0; /* Use PLL programming sequence to */ IDLE;...
Page 986 Programming Examples 18-28 ADSP-BF537 Blackfin Processor Hardware Reference...
Page 987 19 SYSTEM RESET AND BOOTING When the input signal releases, the processor starts fetching and RESET executing instructions from either off-chip asynchronous memory or from the on-chip boot ROM. The internal boot ROM includes a small boot kernel that loads applica- tion data from an external memory or host device.
Page 988: Reset And Powerup
Reset and Powerup Table 19-1. Reset Vector Addresses Boot Source BMODE[2:0] Execution Start Address Bypass boot ROM; execute from 16-bit external 0x2000 0000 memory connected to ASYNC Bank 0 Use boot ROM to boot from 8-bit or 16-bit mem- 0xEF00 0000 ory (PROM/flash) Reserved 0xEF00 0000...
Page 989 System Reset and Booting Table 19-2. Resets Reset Source Result Hardware reset The RESET pin causes a Resets both the core and the peripherals, hardware reset. including the Dynamic Power Management Controller (DPMC). Resets the no boot on software reset bit in SYSCR.
Page 990: System Reset Configuration Register (Syscr)
Reset and Powerup A hardware-initiated reset results in a system-wide reset that includes both core and peripherals. After the pin is deasserted, the processor RESET ensures that all asynchronous peripherals have recognized and completed a reset. After the reset, the processor transitions into the boot mode sequence configured by the state.
Page 991: Software Resets And Watchdog Timer
System Reset and Booting System Reset Configuration Register (SYSCR) X - state is initialized from mode pins during hardware reset 15 14 13 12 11 10 0xFFC0 0104 Reset = dependent on pin values NOBOOT (No Boot on Software BMODE[2:0] (Boot Mode) - RO Reset) 000 - Bypass boot ROM, 0 - Use BMODE to determine...
Page 992: Software Reset Register (Swrst)
Reset and Powerup When L1 instruction memory is configured as cache, make sure the sys- tem software reset sequence has been read into the cache. After either the watchdog or system software reset is initiated, the proces- sor ensures that all asynchronous peripherals have recognized and completed a reset.
Page 993: Core-Only Software Reset
System Reset and Booting Software Reset Register (SWRST) 15 14 13 12 11 10 0xFFC0 0100 Reset = 0x0000 SYSTEM_RESET (System RESET_SOFTWARE Software Reset) (Software Reset 0x0 – 0x6 - No SW reset Status - RO 0x7 - Triggers SW reset 0 - No SW reset since last DOUBLE_FAULT (Core SWRST read...
Page 994: Core And System Reset
Reset and Powerup Core and System Reset To perform a system and core reset, use the code sequence shown in Listing 19-1. Listing 19-1. Core and System Reset /* Issue system soft reset */ P0.L = LO(SWRST) ; P0.H = HI(SWRST) ; R0.L = 0x0007 ;...
Page 995: Servicing Reset Interrupts
System Reset and Booting is set, the register is not modified by the boot kernel on software EVT1 resets. Therefore, programs can control the reset vector for software resets through the register. EVT1 Neither hardware nor the kernel initializes the register in no-boot EVT1 mode.
Page 996 Reset and Powerup Listing 19-3. Exiting Reset by Staying in Supervisor Mode _reset: P0.L = LO(EVT15) ; /* Point to IVG15 in Event Vector Table */ P0.H = HI(EVT15) ; P1.L = LO(_isr_IVG15) ; /* Point to start of IVG15 code */ P1.H = HI(_isr_IVG15) ;...
Page 997: Booting Process
System Reset and Booting The reset handler most likely performs additional tasks not shown in the examples above. Stack pointers and registers are initialized here. EVTx As the boot kernel is running at reset interrupt priority, NMI events, hardware errors and exceptions are not served at boot time. As soon as the reset service routine returns, the processor may ser- vice the events that occurred during the boot sequence.
Page 998 Booting Process .ASM/.C/.CPP .DOJ(s) .DXE(s) ASSEMBLER SOURCE AND/OR LINKER LOADER FILES COMPILER .LDR TARGET SYSTEM BOOTING EXTERNAL UPON RESET MEMORY ADSP-BF534/ADSP-BF536/ ADSP-BF537 PROCESSOR Figure 19-3. Project Flow for a Standalone System Figure 19-4 shows the boot stream contained in a flash memory device, which could be of parallel or serial type.
Page 999: Header Information
System Reset and Booting .LDR FILE ADSP-BF534/BF536/BF537 FLASH/PROM 10-BYTE HEADER FOR BLOCK 1 PROCESSOR LI MEMORY BLOCK 1 BLOCK 1 BLOCK 3 10-BYTE HEADER FOR BLOCK 2 APPLICATION CODE/DATA BLOCK 2 10-BYTE HEADER FOR BLOCK 3 0xEF00 0000 ON-CHIP BLOCK 3 BOOT ROM SDRAM 10-BYTE HEADER FOR BLOCK n...
Page 1000 Booting Process 10-BYTE HEADER FOR BLOCK 1 BLOCK 1 32-BIT ADDRESS 10-BYTE HEADER FOR BLOCK 2 32-BIT COUNT BLOCK 2 16-BIT FLAG 10-BYTE HEADER FOR BLOCK 3 BLOCK 3 . . . 10-BYTE HEADER FOR BLOCK n Figure 19-5. 10-Byte Header Contents Figure 19-6 shows the individual flag word bits.