Modes Of Operation - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Modes of Operation

The following sections provide a functional description of the gen-
eral-purpose timers in various operating modes.
Pulse Width Modulation (PWM_OUT) Mode
Use the
PWM_OUT
interval timing or for periodic interrupt generation.
mode.
PWM_OUT
Setting the
TMODE
(
TIMERx_CONFIG
is an output, but it can be disabled by setting the
configuration register.
In mode, the bits
PWM_OUT
,
CLK_SEL EMU_RUN
may be set individually or in any combination, although some combina-
tions are not useful (such as
PERIOD_CNT = 0
Once a timer has been enabled, the timer counter register is loaded with a
starting value. If
, it is reset to 0x0 as in
CLK_SEL = 1
upward to the value of the timer period register. For either setting of
, when the timer counter equals the timer period, the timer
CLK_SEL
counter is reset to 0x1 on the next clock.
In mode, the
PWM_OUT
one pulse or many pulses. When
pulse mode), the timer uses the
asserting and one deasserting edge, then generates an interrupt (if enabled)
and stops. When
timer uses both the
ADSP-BF537 Blackfin Processor Hardware Reference
mode for PWM signal or single-pulse generation, for
field to b#01 in the timer configuration
) register enables
PWM_OUT
PULSE_HI
, and
TOGGLE_HI
TOGGLE_HI = 1
).
, the timer counter starts at 0x1. If
CLK_SEL = 0
PERIOD_CNT
PERIOD_CNT
TIMERx_WIDTH
is set (
PERIOD_CNT
TIMERx_PERIOD
General-Purpose Timers
Figure 15-4
mode. Here, the timer
OUT_DIS
, ,
PERIOD_CNT IRQ_ENA
enable orthogonal functionality. They
with
OUT_DIS = 1
mode. The timer counts
EXT_CLK
bit controls whether the timer generates
is cleared (
register, generates one
continuous pulse mode), the
PWM_OUT
and
TIMERx_WIDTH
illustrates
pin
TMRx
bit in the timer
, ,
OUT_DIS
or
single
PWM_OUT
registers and
15-13