Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 726

Interface Overview
Tx REGISTER
Tx FIFO
4 x 32 OR 8 x 16
Tx PRI
HOLD REG
COMPANDING
HARDWARE
Tx PRI
SHIFT REG
DT PR I
NOTE 1: ALL WIDE ARROW DATA PATHS ARE 16 OR 32 BITS WIDE, DEPENDING ON SLEN. FOR SLEN = 2 TO 15, A 16-BIT
DATA PATH WITH 8-DEEP FIFO IS USED. FOR SLEN = 16 TO 31, A 32-BIT DATA PATH WITH 4-DEEP FIFO IS USED.
NOTE 2: Tx REGISTER IS THE BOTTOM OF THE Tx FIFO, Rx REGISTER IS THE TOP OF THE Rx FIFO.
Figure 12-1. SPORT Block Diagram
A SPORT receives serial data on its
mits serial data on its
transmit simultaneously for full-duplex operation. For transmit, the data
bits ( and
DTxPRI
For receive, the data bits (
receive clock (
RSCLKx
ates it, or an input if the clock is externally generated. Frame
synchronization signals
serial data word or stream of serial words.
12-6
Tx SEC
HOLD REG
Tx SEC
SHIFT REG
DT SE C TFS TSCLK
and
DTxPRI
) are synchronous to the transmit clock (
DTxSEC
DRxPRI
). The serial clock is an output if the processor gener-
and
RFSx
ADSP-BF537 Blackfin Processor Hardware Reference
PAB
DAB
SERIAL
CONTROL
INTERNAL
CLOCK
GENERATOR
RSCLK RFS
and
DRxPRI DRxSEC
outputs. It can receive and
DTxSEC
and ) are synchronous to the
DRxSEC
are used to indicate the start of a
TFSx
Rx REGISTER
Rx FIFO
4 x 32 OR 8 x 16
Rx PRI Rx SEC
HOLD REG HOLD REG
COMPANDING
HARDWARE
Rx PRI Rx SEC
SHIFT REG SHIFT REG
DR PR I DR SEC
inputs and trans-
TSCLKx
).