Emac_Systat Register - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

EMAC_SYSTAT Register

The
EMAC_SYSTAT
rupt status bits that signal the occurrence of significant Ethernet events to
the application. Detailed descriptions of the functionality can be found in
the section entitled
MAC System Status Register (EMAC_SYSTAT)
0xFFC0 3064
STMDONE (Station Management
Transfer Done Interrupt Status) -
W1C
TXDMAERR (TX DMA Direction
Error Status) - W1C
RXDMAERR (RX DMA Direc-
tion Error Status) - W1C
WAKEDET (Wake-up
Detected Status) - RO
Figure 8-33. MAC System Status Register
Additional information for the
• Station management transfer done interrupt status (
This bit is set when a station management transfer on
MDC/MDIO has completed, provided the
control bit is set in the
ADSP-BF537 Blackfin Processor Hardware Reference
register, shown in
"Ethernet Event Interrupts" on page
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
EMAC_SYSTAT
EMAC_STAADD
Figure 8-33, contains a range of inter-
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0
register bits includes:
STAIE
register.
Ethernet MAC
8-38.
Reset = 0x0000 0000
0
0
0
PHYINT (PHYINT Interrupt
Status) - W1C
MMCINT (MMC Counter
Interrupt Status) - RO
RXFSINT (RX Frame-Status
Interrupt Status) - RO
TXFSINT (TX Frame-Status
Interrupt Status) - RO
)
STMDONE
interrupt enable
8-95