Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 973

interrupts are needed immediately after reset, it is recommended to write
to
RTC_ICTL 0x0000
intended.
Interrupt status can be determined by reading the RTC interrupt status
register (
RTC_ISTAT
responding event, each bit remains set until cleared by a software write to
this register. Event flags are always set; they are not masked by the inter-
rupt enable bits in
respective bit location, except for the write pending status bit, which is
read-only. Writes of 0 to any bit of the register have no effect. This regis-
ter is cleared at reset and during deep sleep.
The RTC interrupt is set whenever an event latched into the
register is enabled in the
cleared whenever all enabled and set bits in
all bits in
RTC_ICTL
As shown in Figure
to the processor core for event handling and wakeup from a sleep state.
The RTC generates a separate signal for wakeup from a deep sleep or from
an internal V
dd
at the 1 Hz tick when any RTC interval event enabled in
The assertion of the deep sleep wakeup signal causes the processor core
clock ( ) and the system clock (
CCLK
asserts the RTC deep sleep wakeup signal also causes the RTC IRQ to
assert once
SCLK
ADSP-BF537 Blackfin Processor Hardware Reference
so that later read-modify-write accesses function as
). All bits in
RTC_ISTAT
. Values are cleared by writing a 1 to the
RTC_ICTL
RTC_ICTL
corresponding to pending events are cleared.
18-3, the RTC generates an interrupt request (IRQ)
power-off state. The deep sleep wakeup signal is asserted
restarts.
are sticky. Once set by the cor-
register. The pending RTC interrupt is
RTC_ISTAT
) to restart. Any enabled event that
SCLK
Real-Time Clock
RTC_ISTAT
are cleared, or when
occurs.
RTC_ICTL
18-15