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• For voltage regulator examples:
• In the ASM examples, P0 points to the voltage regulator
control register (
• In the C examples, the appropriate headers are included and
three data elements are declared, as follows.
#include <cdefBF537.h>
*pREGISTER_NAME labels */
#include <ccblkfn.h>
Blackfin assembler commands */
int
rarily store IMASK */
short
porarily store VR_CTL */
short
VLEV field */
• The CAN, RTC/
enabled as wakeup signals.
Active Mode to Full On Mode
Listing 20-3
and
operating mode to full on mode, in Blackfin assembly and C code,
respectively.
Listing 20-3. Transitioning From Active Mode to Full On Mode (ASM)
CLI R2;
/* disable interrupts, copy IMASK to R2 */
R1.L = 0x3E00;
W[P0] = R1;
ADSP-BF537 Blackfin Processor Hardware Reference
VR_CTL
IMASK_reg;
VR_CTL_reg;
VLEV_field;
RESET
Listing 20-4
provide code for transitioning from active
/* clear BYPASS bit */
/* and write to PLL_CTL */
Dynamic Power Management
).
/* sets up MMR access via
/* contains intrinsics for
/* 32-bit data element to tempo-
/* 16-bit data element to tem-
/* 16-bit data element for
, and PHY/GP wakeup interrupts are
20-29
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