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SPORT Registers
SPORTx_TX Register
The SPORTx transmit data register (
Reads produce a Peripheral Access Bus (PAB) error. Writes to this register
cause writes into the transmitter FIFO. The 16-bit wide FIFO is 8 deep
for word length <= 16 and 4 deep for word length > 16. The FIFO is com-
mon to both primary and secondary data and stores data for both. Data
ordering in the FIFO is shown in the
ter is shown in
ONLY PRIMARY ENABLED
DATA LENGTH <= 16 BITS
8 WORDS OF
PRIMARY DATA
IN FIFO
ONLY PRIMARY ENABLED
DATA LENGTH > 16 BITS
4 WORDS OF
PRIMARY DATA
IN FIFO
Figure 12-29. SPORT Transmit FIFO Data Ordering
It is important to keep the interleaving of primary and secondary data in
the FIFO as shown. This means that PAB/DMA writes to the FIFO must
follow an order of primary first, and then secondary, if secondary is
enabled. DAB/PAB writes must match their size to the data word length.
For word length up to and including 16 bits, use a 16-bit write. Use a
32-bit write for word length greater than 16 bits.
12-58
Figure
12-30.
15
0
PRIMARY
W7
PRIMARY
W6
W5
PRIMARY
W4
PRIMARY
W3
PRIMARY
PRIMARY
W2
W1
PRIMARY
W0
PRIMARY
15
0
PRIMARY
W3 LOW
PRIMARY
W3 HIGH
W2 LOW
PRIMARY
W2 HIGH
PRIMARY
W1 LOW
PRIMARY
PRIMARY
W1 HIGH
W0 LOW
PRIMARY
W0 HIGH
PRIMARY
ADSP-BF537 Blackfin Processor Hardware Reference
) is a write-only register.
SPORTx_TX
Figure
12-29. The
PRIMARY AND
SECONDARY ENABLED
DATA LENGTH <= 16 BITS
4 WORDS OF
PRIMARY DATA AND
4 WORDS OF
SECONDARY DATA
IN FIFO
PRIMARY AND
SECONDARY ENABLED
DATA LENGTH > 16 BITS
2 WORDS OF
PRIMARY DATA AND
2 WORDS OF
SECONDARY DATA
IN FIFO
regis-
SPORTx_TX
15
0
SECONDARY
W3
PRIMARY
W3
SECONDARY
W2
W2
PRIMARY
SECONDARY
W1
PRIMARY
W1
SECONDARY
W0
PRIMARY
W0
15
0
SECONDARY
W1 LOW
SECONDARY
W1 HIGH
W1 LOW
PRIMARY
W1 HIGH
PRIMARY
SECONDARY
W0 LOW
SECONDARY
W0 HIGH
W0 LOW
PRIMARY
W0 HIGH
PRIMARY
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