Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1166

Index
booting
initialization code, 19-22
Intel hex loader file,
loader file utility, 19-59
memory locations, 19-12
multi-DXE, 19-26
PORTF_FER, 19-20
PORT_MUX, 19-20
slave boot modes, 19-19
SPI master boot from flash,
SPI master mode, 19-42
SPI slave mode, 19-48
TWI master boot from flash,
TWI master mode, 19-53
TWI slave mode, 19-55
UART slave mode, 19-56
boot kernel, 19-1
boot modes, 1-25
boot ROM
internal, 19-1
memory space, 3-8
_BOOTROM_Boot_DXE_SPI function,
19-31
_BOOTROM_Get_DXE_Address_SPI
function, 19-31
boot stream, 19-1, 19-11
boundary-scan architecture,
boundary-scan register,
BroadcastFramesReceivedOK register,
8-56
BroadcastFramesXmittedOK register,
broadcast mode, 10-10, 10-17,
BRP[9:0] field, 9-10, 9-45
BR signal, 6-8
buffer registers, timers,
BUFRDERR bit, 11-13,
BUFWRERR bit, 11-13,
I-4
(continued)
19-38
19-28
19-29
B-2
B-6
8-62
10-18
15-47
11-38
11-38
ADSP-BF537 Blackfin Processor Hardware Reference
burst length, 6-33, G-2
burst type, 6-34, G-2
bus agents
DAB, 2-9
PAB, 2-6
BUSBUSY bit, 11-12,
bus contention, avoiding, 6-11,
bus cycles
asynchronous read, 6-13
asynchronous write,
bus error, EBIU, 6-7
buses
See also DAB, DCB, DEB, EAB, EPB,
PAB
bandwidth, 1-2
core, 2-4
and DMA, 5-45
hierarchy, 2-3
on-chip, 2-1
PAB, 2-6
peripheral, 2-6
and peripherals, 1-2
prioritization and DMA,
busmastership, granting to external SDC,
6-46
bus-off interrupt, CAN,
bus request and grant,
2
bus standard, I C, 1-11
BYPASS bit, 20-26
bypass capacitor placement,
BYPASS instruction, B-6
bypass mode, 19-34
bypass register, B-6
byte address, 6-64
byte enables, 6-18
byte enable x bit, 8-85, 8-86, 8-87,
11-38
21-7
6-14
5-53
9-25
6-8
21-11
8-88