Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1050

Phase Locked Loop and Clock Control
The reset value of
in the boot code.
Table 20-1 illustrates the
and settings.
DF
As shown in the table, different combinations of
generate the same
tion may provide lower power or satisfy the
Under normal conditions, setting
dissipation. See the processor data sheet for maximum and minimum fre-
quencies for
CLKIN
Table 20-1. MSEL Encodings
Signal name
MSEL[5:0]
0
1
2
N = 3–62
63
The PLL control register (
Figure 20-5 on page
not take effect immediately. In general, the
grammed with a new value, and then a specific PLL programming
sequence must be executed to implement the changes. See
ming Sequence" on page
20-4
is 0xA. This value can be reprogrammed at startup
MSEL
multiplication factors for the various
VCO
frequencies. For a given application, one combina-
VCO
, , and
CCLK VCO.
VCO Frequency
DF = 0 DF = 1
64x 32x
1x 0.5x
2x 1x
Nx 0.5Nx
63x 31.5x
PLL_CTL
20-26). Note that changes to the
20-15.
ADSP-BF537 Blackfin Processor Hardware Reference
MSEL[5:0]
maximum frequency.
VCO
to 1 typically results in lower power
DF
) controls operation of the PLL (See
PLL_CTL
MSEL
and can
DF
register do
PLL_CTL
register is first pro-
"PLL Program-