Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1216

Index
WAKEDET bit, 8-36, 8-95,
wake from hibernate, MAC,
wake from sleep, MAC,
wakeup filter 0 address type bit, 8-89,
wakeup filter 0 pattern CRC[15:0] field,
8-92
wakeup filter 0 pattern offset[7:0] field,
8-91
wakeup filter 1 address type bit, 8-89,
wakeup filter 1 pattern CRC[15:0] field,
8-92
wakeup filter 1 pattern offset[7:0] field,
8-91
wakeup filter 2 address type bit, 8-89,
wakeup filter 2 pattern CRC[15:0] field,
8-92
wakeup filter 2 pattern offset[7:0] field,
8-91
wakeup filter 3 address type bit,
wakeup filter 3 pattern CRC[15:0] field,
8-92
wakeup filter 3 pattern offset[7:0] field,
8-91
wakeup frame detected,
wakeup function, 4-10
wakeup interrupt, CAN,
WAKEUP signal, 20-16
watchdog control register (WDOG_CTL),
17-7, 17-8
watchdog count[15:0] field,
watchdog count[31:16] field,
watchdog count register (WDOG_CNT),
17-5, 17-6
watchdog mode, CAN,
watchdog status[15:0] field,
watchdog status[31:16] field,
watchdog status register (WDOG_STAT),
17-6, 17-7
I-54
8-96
8-31
8-32
8-90
8-90
8-90
8-89
8-41
9-25
17-6
17-6
9-19
17-7
17-7
ADSP-BF537 Blackfin Processor Hardware Reference
watchdog timer, 1-21,
block diagram, 17-2
disabling, 17-5
and emulation mode,
features, 17-1
registers, 17-5
and reset, 17-4
reset, 19-5
starting, 17-4
zero value, 17-5
waveform generation, pulse width
modulation, 15-16
WBA bit, 9-43
WDEN[7:0] field, 17-7
WDEV[1:0] field, 17-3,
WDOG_CNT (watchdog count register),
17-3, 17-5, 17-6
WDOG_CTL (watchdog control register),
17-7, 17-8
WDOG_STAT (watchdog status register),
17-3, 17-6, 17-7
WDSIZE[1:0] field, 5-74,
WDTH_CAP mode, 15-26,
control bit and register usage,
WLS[1:0] field, 13-21
WNR bit, 5-74, 5-78
WOFF[9:0] field, 12-22,
WOM bit, 10-17, 10-41
word length
SPI, 10-18
SPORT, 12-28
SPORT receive data,
SPORT transmit data,
work unit
completion, 5-25
DMA, 5-17
interrupt timing, 5-28
restrictions, 5-27
transitions, 5-27
WR bit, 9-44
17-1 to 17-10
17-2
17-7
5-77
15-47
15-50
12-66
12-61
12-58