Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1180

Index
EXTEST instruction, B-5
EXTID[15:0] field, 9-51,
EXTID[17:16] field, 9-49,
EXTIF bit, 9-24, 9-48
EXTIM bit, 9-24, 9-47
EXTIS bit, 9-24, 9-47
EZ-KIT Lite, 1-31
F
FAST bit, 11-34, 11-36
fast mode, TWI, 11-10
FBBRW bit, 6-68, 6-76
FDF bit, 9-18, 9-49
FDMODE bit, 8-64, 8-65
FE bit, 13-24, 13-25
FER bit, 9-85
FFE bit, 13-31, 13-32
field, 3-8
FIFO, 6-1
filtering, MAC, 8-13
FINAL bit, 19-14
finish control command, DMA,
flag word register, 19-14
flash interface, 21-5
flash memory, 1-6, 6-1
FLCBUSY bit, 8-79, 8-80
FLCE bit, 8-16, 8-79,
FLCPAUSE[15:0] field,
FLD bit, 7-31, 7-33
FLD_SEL bit, 7-5, 7-27,
flex descriptors, 5-3
FLGx bit, 10-42, 10-43
FLOW[2:0] field, 5-25, 5-27, 5-60, 5-74,
5-75
flow charts
boot block flag processing,
CAN receive operation,
CAN transmit operation,
DMA, 5-21, 5-22
I-18
9-55
9-53
5-36
8-80
8-79
7-30
19-18
9-17
9-14
ADSP-BF537 Blackfin Processor Hardware Reference
flow charts
general-purpose timers interrupt
structure, 15-9
GPIO, 14-20
GPIO interrupt generation,
PPI, 7-25
SPI core-driven, 10-36
SPI DMA, 10-37
timer EXT_CLK mode,
timer PWM_OUT mode,
timer WDTH_CAP mode,
TWI master mode, 11-29
TWI slave mode, 11-28
FLOW mode, DMA, 5-19
FLOW value, DMA, 5-23
FLSx bit, 10-10, 10-42
FMD bit, 9-49
FPE bit, 13-31, 13-32
frame buffer,Ethernet,
FrameCheckSequenceErrors register,
framed serial transfers, characteristics,
12-31
framed/unframed data,
frame filter evaluation, MAC,
FramesAbortedDueToXSColls register,
8-61
FramesLen1024_MaxReceived register,
8-60
FramesLen128_255Received register,
FramesLen256_511Received register,
FramesLen512_1023Received register,
8-60
FramesLen65_127Received register,
FramesLen65_127Transmitted register,
8-63
FramesLenEq64Received register,
FramesLenEq64Transmitted register,
FramesLenLt64Received register,
FramesLostDueToIntMAC RcvError
register, 8-55
(continued)
14-17
15-35
15-14
15-27
8-128
8-55
12-31
8-15
8-59
8-60
8-59
8-59
8-63
8-59