Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1164

Index
AMC, 1-6, 1-9
bus contention, 6-11
EBIU block diagram,
features, 6-9
signals, 6-10
timing parameters, 6-20
AMCKEN bit, 6-19, 6-21
AME bit, 9-53
AMIDE bit, 9-49
AMS, 6-10
ANAK bit, 11-14, 11-38
application data, loading,
arbitration
DAB, 2-8, 2-9
DCB, 2-8, 2-9
DEB, 2-8, 2-9
EAB, 2-11
latency, 2-10
TWI, 11-7
architecture, memory,
ARDY pin, 6-12, 6-16
array access bit, 3-10
ASIC/FPGA designs, 6-1
ASTP bit, 8-17, 8-64,
asynchronous controller,
asynchronous FIFO connection,
asynchronous interfaces supported,
asynchronous memory, 3-2, 6-2,
asynchronous memory bank address range
(table), 6-10
asynchronous memory bank control 0
register (EBIU_AMBCTL0),
asynchronous memory bank control 1
register (EBIU_AMBCTL1),
asynchronous memory bank control
registers (EBIU_AMBCTLx),
asynchronous memory controller, See AMC
asynchronous memory global control
register (EBIU_AMGCTL),
asynchronous read, 6-13
I-2
6-4
19-1
3-1
8-70
1-9
5-42
6-1
6-9
6-22
6-23
6-21
6-18
ADSP-BF537 Blackfin Processor Hardware Reference
asynchronous serial communications,
asynchronous write, 6-14
ASYNC memory banks,
autobaud, and general-purpose timers,
15-34
autobaud detection, 13-4, 13-13,
autobuffer mode, 5-14, 5-31,
auto-refresh
command, 6-35, 6-52
timing, 6-60
auto-transmit mode, CAN,
avoiding bus contention,
B
B0HT[1:0] field, 6-22
B0RAT[3:0] field, 6-22
B0RDYEN bit, 6-22
B0RDYPOL bit, 6-22
B0ST[1:0] field, 6-22
B0TT[1:0] field, 6-22
B0WAT[3:0] field, 6-22
B1HT[1:0] field, 6-22
B1RAT[3:0] field, 6-22
B1RDYEN bit, 6-22
B1RDYPOL bit, 6-22
B1ST[1:0] field, 6-22
B1TT[1:0] field, 6-22
B1WAT[3:0] field, 6-22
B2HT[1:0] field, 6-23
B2RAT[3:0] field, 6-23
B2RDYEN bit, 6-23
B2RDYPOL bit, 6-23
B2ST[1:0] field, 6-23
B2TT[1:0] field, 6-23
B2WAT[3:0] field, 6-23
B3HT[1:0] field, 6-23
B3RAT[3:0] field, 6-23
B3RDYEN bit, 6-23
B3RDYPOL bit, 6-23
B3ST[1:0] field, 6-23
13-4
6-3
15-34
5-76
9-15
6-11