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Software Reset Register (SWRST)
0xFFC0 0100
RESET_SOFTWARE
(Software Reset
Status - RO
0 - No SW reset since last
SWRST read
1 - SW reset occurred since
last SWRST read
RESET_WDOG (Software
Watchdog Timer Source)
- RO
0 - SW reset not generated by
watchdog
1 - SW reset generated by
watchdog
RESET_DOUBLE (Core
Double Fault Reset) - RO
0 - SW reset not generated
by double fault
1 - SW reset generated by
double fault
Figure 19-2. Software Reset Register
Core-Only Software Reset
A core-only software reset is initiated by executing the
or by setting the software reset (
ister (
) via emulation software through the JTAG port. (
DBGCTL
not visible to the memory map.)
A core-only software reset affects only the state of the core. Note the sys-
tem resources may be in an undetermined or even unreliable state,
depending on the system activity during the reset period.
ADSP-BF537 Blackfin Processor Hardware Reference
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
SYSRST
System Reset and Booting
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RAISE 1
) bit in the core debug control reg-
Reset = 0x0000
SYSTEM_RESET (System
Software Reset)
0x0 – 0x6 - No SW reset
0x7 - Triggers SW reset
DOUBLE_FAULT (Core
Double Fault Reset
Enable)
0 - No reset caused by
Core Double Fault
1 - Reset generated upon
Core Double Fault
instruction
is
DBGCTL
19-7
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