Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1171

configuration
CAN, 9-12
regulator wakeups, 20-32
SDC, 6-56
SDRAM, 6-25
SPORT, 12-11
congestion, on DMA channels,
contention, bus, avoiding,
continuous polling, and MMC register,
8-44
continuous transition, DMA,
control bit summary, general-purpose
timers, 15-50
control byte sequences, PPI,
control frames, MAC,
controller area network, See CAN
control register
data memory, 3-9
EBIU, 6-6
conventions, -lv
core
block diagram, 2-5
core bus, 2-4
core clock (CCLK), 20-5,
core clock/system clock ratio control,
20-5
powering down, 20-22
waking from idle state,
core and system reset, code example,
core clock, See CCLK
core event controller (CEC), 4-1,
core-only software reset, 19-3,
core timer, 16-1 to 16-8
block diagram, 16-2
clock rate, 16-1
features, 16-1
initialization, 16-2
internal interfaces, 16-2
interrupts, 16-3
ADSP-BF537 Blackfin Processor Hardware Reference
5-50
6-11
5-30
7-9
8-16
21-2
4-9
19-8
4-2
19-7
core timer
low power mode, 16-3
operation, 16-2
registers, 16-4
scaling, 16-7
core timer control register (TCNTL), 16-3,
16-4
core timer count register (TCOUNT),
16-5
core timer period register (TPERIOD),
16-6
core timer scale register (TSCALE),
core voltage, changing,
counter, RTC, 18-1
count value[15:0] field,
count value[31:16] field,
CPHA bit, 10-41
CPOL bit, 10-41
CRC-16 hash value calculation,
CRC-32 calculation, MAC,
CRCE bit, 9-85
CRC state, MAC, 8-37
CROLL bit, 8-44, 8-124,
CrossCore software, 1-29
crosstalk, 21-9
CSA bit, 9-37, 9-44
CSEL[1:0] field, 20-5,
CSR bit, 9-37, 9-43
CTYPE bit, 5-71
current address field, 5-84
current address registers
(DMAx_CURR_ADDR),
(MDMA_yy_CURR_ADDR),
current descriptor pointer field,
current descriptor pointer registers
(DMAx_CURR_DESC_PTR),
(MDMA_yy_CURR_DESC_PTR),
5-96
Index
(continued)
16-7
20-33
16-5
16-5
8-38
8-73
8-125
20-25
5-83
5-83
5-97
5-96
I-9